[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v12 10/11] hmat acpi: Build Memory Side Cache Information Str
From: |
Igor Mammedov |
Subject: |
Re: [PATCH v12 10/11] hmat acpi: Build Memory Side Cache Information Structure(s) |
Date: |
Fri, 4 Oct 2019 10:01:57 +0200 |
On Fri, 20 Sep 2019 15:43:48 +0800
Tao Xu <address@hidden> wrote:
> From: Liu Jingqi <address@hidden>
>
> This structure describes memory side cache information for memory
> proximity domains if the memory side cache is present and the
> physical device forms the memory side cache.
> The software could use this information to effectively place
> the data in memory to maximize the performance of the system
> memory that use the memory side cache.
>
> Reviewed-by: Daniel Black <address@hidden>
> Reviewed-by: Jonathan Cameron <address@hidden>
> Signed-off-by: Liu Jingqi <address@hidden>
> Signed-off-by: Tao Xu <address@hidden>
> ---
>
> No changes in v12.
>
> Changes in v11:
> - Move numa option patches forward.
> ---
> hw/acpi/hmat.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 63 insertions(+), 1 deletion(-)
>
> diff --git a/hw/acpi/hmat.c b/hw/acpi/hmat.c
> index e7be849581..6b260eeef5 100644
> --- a/hw/acpi/hmat.c
> +++ b/hw/acpi/hmat.c
> @@ -160,13 +160,62 @@ static void build_hmat_lb(GArray *table_data,
> HMAT_LB_Info *hmat_lb,
> }
> }
>
> +/* ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure: Table 5-147 */
> +static void build_hmat_cache(GArray *table_data, HMAT_Cache_Info *hmat_cache)
> +{
> + /*
> + * Cache Attributes: Bits [3:0] – Total Cache Levels
> + * for this Memory Proximity Domain
> + */
> + uint32_t cache_attr = hmat_cache->total_levels & 0xF;
> +
> + /* Bits [7:4] : Cache Level described in this structure */
> + cache_attr |= (hmat_cache->level & 0xF) << 4;
> + /* Bits [11:8] - Cache Associativity */
> + cache_attr |= (hmat_cache->associativity & 0xF) << 8;
> +
> + /* Bits [15:12] - Write Policy */
> + cache_attr |= (hmat_cache->write_policy & 0xF) << 12;
s/0xF/0x7/ for Cache Associativity / Write Policy
> +
> + /* Bits [31:16] - Cache Line size in bytes */
> + cache_attr |= (hmat_cache->line_size & 0xFFFF) << 16;
> +
> + cache_attr = cpu_to_le32(cache_attr);
> +
> + /* Type */
> + build_append_int_noprefix(table_data, 2, 2);
> + /* Reserved */
> + build_append_int_noprefix(table_data, 0, 2);
> + /* Length */
> + build_append_int_noprefix(table_data, 32, 4);
> + /* Proximity Domain for the Memory */
> + build_append_int_noprefix(table_data, hmat_cache->mem_proximity, 4);
> + /* Reserved */
> + build_append_int_noprefix(table_data, 0, 4);
> + /* Memory Side Cache Size */
> + build_append_int_noprefix(table_data, hmat_cache->size, 8);
> + /* Cache Attributes */
> + build_append_int_noprefix(table_data, cache_attr, 4);
> + /* Reserved */
> + build_append_int_noprefix(table_data, 0, 2);
> + /*
> + * Number of SMBIOS handles (n)
> + * Linux kernel uses Memory Side Cache Information Structure
> + * without SMBIOS entries for now, so set Number of SMBIOS handles
> + * as 0.
> + */
> + build_append_int_noprefix(table_data, 0, 2);
> +}
> +
> /* Build HMAT sub table structures */
> static void hmat_build_table_structs(GArray *table_data, NumaState *nstat)
> {
> uint16_t flags;
> uint32_t *initiator_list = NULL;
> - int i, j, hrchy, type;
> + int i, j, hrchy, type, level;
s/level/cache_level/
> HMAT_LB_Info *numa_hmat_lb;
> + HMAT_Cache_Info *numa_hmat_cache;
>
> for (i = 0; i < nstat->num_nodes; i++) {
> flags = 0;
> @@ -205,6 +254,19 @@ static void hmat_build_table_structs(GArray *table_data,
> NumaState *nstat)
> }
> }
>
> + /*
> + * ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure:
> + * Table 5-147
> + */
> + for (i = 0; i < nstat->num_nodes; i++) {
> + for (level = 0; level <= MAX_HMAT_CACHE_LEVEL; level++) {
> + numa_hmat_cache = nstat->hmat_cache[i][level];
> + if (numa_hmat_cache) {
> + build_hmat_cache(table_data, numa_hmat_cache);
> + }
> + }
> + }
> +
> g_free(initiator_list);
> }
>
[Prev in Thread] |
Current Thread |
[Next in Thread] |
- Re: [PATCH v12 10/11] hmat acpi: Build Memory Side Cache Information Structure(s),
Igor Mammedov <=