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[PATCH v7 11/22] tcg/ppc: Add support for vector saturated add/subtract
From: |
Richard Henderson |
Subject: |
[PATCH v7 11/22] tcg/ppc: Add support for vector saturated add/subtract |
Date: |
Mon, 30 Sep 2019 13:21:14 -0700 |
Add support for vector saturated add/subtract using Altivec
instructions:
VADDSBS, VADDSHS, VADDSWS, VADDUBS, VADDUHS, VADDUWS, and
VSUBSBS, VSUBSHS, VSUBSWS, VSUBUBS, VSUBUHS, VSUBUWS.
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c | 36 ++++++++++++++++++++++++++++++++++++
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 13699f1b63..3ebbbfa77e 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -163,7 +163,7 @@ extern bool have_altivec;
#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 0
-#define TCG_TARGET_HAS_sat_vec 0
+#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 0
#define TCG_TARGET_HAS_cmpsel_vec 0
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 6cfc78bb59..a1165209fc 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -471,12 +471,24 @@ static int tcg_target_const_match(tcg_target_long val,
TCGType type,
#define STVX XO31(231)
#define STVEWX XO31(199)
+#define VADDSBS VX4(768)
+#define VADDUBS VX4(512)
#define VADDUBM VX4(0)
+#define VADDSHS VX4(832)
+#define VADDUHS VX4(576)
#define VADDUHM VX4(64)
+#define VADDSWS VX4(896)
+#define VADDUWS VX4(640)
#define VADDUWM VX4(128)
+#define VSUBSBS VX4(1792)
+#define VSUBUBS VX4(1536)
#define VSUBUBM VX4(1024)
+#define VSUBSHS VX4(1856)
+#define VSUBUHS VX4(1600)
#define VSUBUHM VX4(1088)
+#define VSUBSWS VX4(1920)
+#define VSUBUWS VX4(1664)
#define VSUBUWM VX4(1152)
#define VMAXSB VX4(258)
@@ -2844,6 +2856,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_smin_vec:
case INDEX_op_umax_vec:
case INDEX_op_umin_vec:
+ case INDEX_op_ssadd_vec:
+ case INDEX_op_sssub_vec:
+ case INDEX_op_usadd_vec:
+ case INDEX_op_ussub_vec:
return vece <= MO_32;
case INDEX_op_cmp_vec:
return vece <= MO_32 ? -1 : 0;
@@ -2945,6 +2961,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 },
gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 },
gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 },
+ ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 },
+ usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 },
+ sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 },
+ ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 },
umin_op[4] = { VMINUB, VMINUH, VMINUW, 0 },
smin_op[4] = { VMINSB, VMINSH, VMINSW, 0 },
umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, 0 },
@@ -2971,6 +2991,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_sub_vec:
insn = sub_op[vece];
break;
+ case INDEX_op_ssadd_vec:
+ insn = ssadd_op[vece];
+ break;
+ case INDEX_op_sssub_vec:
+ insn = sssub_op[vece];
+ break;
+ case INDEX_op_usadd_vec:
+ insn = usadd_op[vece];
+ break;
+ case INDEX_op_ussub_vec:
+ insn = ussub_op[vece];
+ break;
case INDEX_op_smin_vec:
insn = smin_op[vece];
break;
@@ -3277,6 +3309,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_andc_vec:
case INDEX_op_orc_vec:
case INDEX_op_cmp_vec:
+ case INDEX_op_ssadd_vec:
+ case INDEX_op_sssub_vec:
+ case INDEX_op_usadd_vec:
+ case INDEX_op_ussub_vec:
case INDEX_op_smax_vec:
case INDEX_op_smin_vec:
case INDEX_op_umax_vec:
--
2.17.1
- [PATCH v7 01/22] tcg/ppc: Introduce Altivec registers, (continued)
- [PATCH v7 01/22] tcg/ppc: Introduce Altivec registers, Richard Henderson, 2019/09/30
- [PATCH v7 02/22] tcg/ppc: Introduce macro VX4(), Richard Henderson, 2019/09/30
- [PATCH v7 03/22] tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC(), Richard Henderson, 2019/09/30
- [PATCH v7 05/22] tcg/ppc: Replace HAVE_ISA_2_06, Richard Henderson, 2019/09/30
- [PATCH v7 06/22] tcg/ppc: Replace HAVE_ISEL macro with a variable, Richard Henderson, 2019/09/30
- [PATCH v7 04/22] tcg/ppc: Create TCGPowerISA and have_isa, Richard Henderson, 2019/09/30
- [PATCH v7 07/22] tcg/ppc: Enable tcg backend vector compilation, Richard Henderson, 2019/09/30
- [PATCH v7 10/22] tcg/ppc: Add support for vector add/subtract, Richard Henderson, 2019/09/30
- [PATCH v7 08/22] tcg/ppc: Add support for load/store/logic/comparison, Richard Henderson, 2019/09/30
- [PATCH v7 09/22] tcg/ppc: Add support for vector maximum/minimum, Richard Henderson, 2019/09/30
- [PATCH v7 11/22] tcg/ppc: Add support for vector saturated add/subtract,
Richard Henderson <=
- [PATCH v7 14/22] tcg/ppc: Support vector dup2, Richard Henderson, 2019/09/30
- [PATCH v7 12/22] tcg/ppc: Support vector shift by immediate, Richard Henderson, 2019/09/30
- [PATCH v7 13/22] tcg/ppc: Support vector multiply, Richard Henderson, 2019/09/30
- [PATCH v7 15/22] tcg/ppc: Enable Altivec detection, Richard Henderson, 2019/09/30
- [PATCH v7 18/22] tcg/ppc: Update vector support for v2.07 VSX, Richard Henderson, 2019/09/30
- [PATCH v7 16/22] tcg/ppc: Update vector support for VSX, Richard Henderson, 2019/09/30
- [PATCH v7 17/22] tcg/ppc: Update vector support for v2.07 Altivec, Richard Henderson, 2019/09/30
- [PATCH v7 19/22] tcg/ppc: Update vector support for v2.07 FP, Richard Henderson, 2019/09/30
- [PATCH v7 20/22] tcg/ppc: Update vector support for v3.00 Altivec, Richard Henderson, 2019/09/30
- [PATCH v7 21/22] tcg/ppc: Update vector support for v3.00 load/store, Richard Henderson, 2019/09/30