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Re: [PATCH] i386: Add CPUID bit for CLZERO and XSAVEERPTR
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From: |
Sebastian Andrzej Siewior |
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Subject: |
Re: [PATCH] i386: Add CPUID bit for CLZERO and XSAVEERPTR |
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Date: |
Thu, 26 Sep 2019 13:21:50 +0200 |
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User-agent: |
NeoMutt/20180716 |
On 2019-09-26 13:06:34 [+0200], Paolo Bonzini wrote:
> On 25/09/19 23:49, Sebastian Andrzej Siewior wrote:
> > #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store
> > Bypass Disable */
> >
> > +#define CPUD_800_008_EBX_CLZERO (1U << 0) /* CLZERO instruction
> > */
> > +#define CPUD_800_008_EBX_XSAVEERPTR (1U << 2) /* Always
> > save/restore FP error pointers */
> > #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and
>
> Well, there are obvious typos here but I can fix them for you.
Sorry for the missing I.
> Which processors have these?
There are mention in AMD document [0]. I *think* there were introduced
in Zen, see them on a Ryzen and Epyc.
[0] https://www.amd.com/system/files/TechDocs/24594.pdf
> Paolo
Sebastian