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[PULL 05/16] cputlb: Split out load/store_memop
From: |
Richard Henderson |
Subject: |
[PULL 05/16] cputlb: Split out load/store_memop |
Date: |
Wed, 25 Sep 2019 11:45:37 -0700 |
We will shortly be using these more than once.
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: David Hildenbrand <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
accel/tcg/cputlb.c | 107 +++++++++++++++++++++++----------------------
1 file changed, 55 insertions(+), 52 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index e31378bce3..eeba8c9847 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1281,6 +1281,29 @@ static void *atomic_mmu_lookup(CPUArchState *env,
target_ulong addr,
typedef uint64_t FullLoadHelper(CPUArchState *env, target_ulong addr,
TCGMemOpIdx oi, uintptr_t retaddr);
+static inline uint64_t QEMU_ALWAYS_INLINE
+load_memop(const void *haddr, MemOp op)
+{
+ switch (op) {
+ case MO_UB:
+ return ldub_p(haddr);
+ case MO_BEUW:
+ return lduw_be_p(haddr);
+ case MO_LEUW:
+ return lduw_le_p(haddr);
+ case MO_BEUL:
+ return (uint32_t)ldl_be_p(haddr);
+ case MO_LEUL:
+ return (uint32_t)ldl_le_p(haddr);
+ case MO_BEQ:
+ return ldq_be_p(haddr);
+ case MO_LEQ:
+ return ldq_le_p(haddr);
+ default:
+ qemu_build_not_reached();
+ }
+}
+
static inline uint64_t QEMU_ALWAYS_INLINE
load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
uintptr_t retaddr, MemOp op, bool code_read,
@@ -1373,33 +1396,7 @@ load_helper(CPUArchState *env, target_ulong addr,
TCGMemOpIdx oi,
do_aligned_access:
haddr = (void *)((uintptr_t)addr + entry->addend);
- switch (op) {
- case MO_UB:
- res = ldub_p(haddr);
- break;
- case MO_BEUW:
- res = lduw_be_p(haddr);
- break;
- case MO_LEUW:
- res = lduw_le_p(haddr);
- break;
- case MO_BEUL:
- res = (uint32_t)ldl_be_p(haddr);
- break;
- case MO_LEUL:
- res = (uint32_t)ldl_le_p(haddr);
- break;
- case MO_BEQ:
- res = ldq_be_p(haddr);
- break;
- case MO_LEQ:
- res = ldq_le_p(haddr);
- break;
- default:
- qemu_build_not_reached();
- }
-
- return res;
+ return load_memop(haddr, op);
}
/*
@@ -1530,6 +1527,36 @@ tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env,
target_ulong addr,
* Store Helpers
*/
+static inline void QEMU_ALWAYS_INLINE
+store_memop(void *haddr, uint64_t val, MemOp op)
+{
+ switch (op) {
+ case MO_UB:
+ stb_p(haddr, val);
+ break;
+ case MO_BEUW:
+ stw_be_p(haddr, val);
+ break;
+ case MO_LEUW:
+ stw_le_p(haddr, val);
+ break;
+ case MO_BEUL:
+ stl_be_p(haddr, val);
+ break;
+ case MO_LEUL:
+ stl_le_p(haddr, val);
+ break;
+ case MO_BEQ:
+ stq_be_p(haddr, val);
+ break;
+ case MO_LEQ:
+ stq_le_p(haddr, val);
+ break;
+ default:
+ qemu_build_not_reached();
+ }
+}
+
static inline void QEMU_ALWAYS_INLINE
store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
TCGMemOpIdx oi, uintptr_t retaddr, MemOp op)
@@ -1657,31 +1684,7 @@ store_helper(CPUArchState *env, target_ulong addr,
uint64_t val,
do_aligned_access:
haddr = (void *)((uintptr_t)addr + entry->addend);
- switch (op) {
- case MO_UB:
- stb_p(haddr, val);
- break;
- case MO_BEUW:
- stw_be_p(haddr, val);
- break;
- case MO_LEUW:
- stw_le_p(haddr, val);
- break;
- case MO_BEUL:
- stl_be_p(haddr, val);
- break;
- case MO_LEUL:
- stl_le_p(haddr, val);
- break;
- case MO_BEQ:
- stq_be_p(haddr, val);
- break;
- case MO_LEQ:
- stq_le_p(haddr, val);
- break;
- default:
- qemu_build_not_reached();
- }
+ store_memop(haddr, val, op);
}
void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
--
2.17.1
- [PULL 00/16] tcg patch queue, Richard Henderson, 2019/09/25
- [PULL 01/16] exec: Use TARGET_PAGE_BITS_MIN for TLB flags, Richard Henderson, 2019/09/25
- [PULL 02/16] cputlb: Disable __always_inline__ without optimization, Richard Henderson, 2019/09/25
- [PULL 03/16] qemu/compiler.h: Add qemu_build_not_reached, Richard Henderson, 2019/09/25
- [PULL 04/16] cputlb: Use qemu_build_not_reached in load/store_helpers, Richard Henderson, 2019/09/25
- [PULL 05/16] cputlb: Split out load/store_memop,
Richard Henderson <=
- [PULL 06/16] cputlb: Introduce TLB_BSWAP, Richard Henderson, 2019/09/25
- [PULL 07/16] exec: Adjust notdirty tracing, Richard Henderson, 2019/09/25
- [PULL 09/16] cputlb: Move NOTDIRTY handling from I/O path to TLB path, Richard Henderson, 2019/09/25
- [PULL 08/16] cputlb: Move ROM handling from I/O path to TLB path, Richard Henderson, 2019/09/25
- [PULL 11/16] cputlb: Merge and move memory_notdirty_write_{prepare, complete}, Richard Henderson, 2019/09/25
- [PULL 12/16] cputlb: Handle TLB_NOTDIRTY in probe_access, Richard Henderson, 2019/09/25
- [PULL 10/16] cputlb: Partially inline memory_region_section_get_iotlb, Richard Henderson, 2019/09/25
- [PULL 13/16] cputlb: Remove cpu->mem_io_vaddr, Richard Henderson, 2019/09/25
- [PULL 14/16] cputlb: Remove tb_invalidate_phys_page_range is_cpu_write_access, Richard Henderson, 2019/09/25
- [PULL 15/16] cputlb: Pass retaddr to tb_invalidate_phys_page_fast, Richard Henderson, 2019/09/25