Re: [PATCH V4] target/riscv: Ignore reserved bits in PTE for RV64

[Bin Meng]

On Wed, Sep 25, 2019 at 5:21 PM <address@hidden> wrote:
>
> From: Guo Ren <address@hidden>
>
> Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
> need to ignore them. They cannot be a part of ppn.
>
> 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
>    4.4 Sv39: Page-Based 39-bit Virtual-Memory System
>    4.5 Sv48: Page-Based 48-bit Virtual-Memory System
>
> Signed-off-by: Guo Ren <address@hidden>
> Reviewed-by: Liu Zhiwei <address@hidden>
> ---
>  target/riscv/cpu_bits.h   | 7 +++++++
>  target/riscv/cpu_helper.c | 2 +-
>  2 files changed, 8 insertions(+), 1 deletion(-)
>
> Changelog V4:
>  - Change title to Ignore not Bugfix
>  - Use PTE_PPN_MASK for RV32 and RV64
>
> Changelog V3:
>  - Use UUL define for PTE_RESERVED
>  - Keep ppn >> PTE_PPN_SHIFT
>
> Changelog V2:
>  - Bugfix pte destroyed cause boot fail
>  - Change to AND with a mask instead of shifting both directions
>

Reviewed-by: Bin Meng <address@hidden>
Tested-by: Bin Meng <address@hidden>