Re: [Qemu-devel] [PATCH v1 1/2] RISC-V: Handle bus errors in the page table walker

[Philippe Mathieu-Daudé]

On 9/18/19 1:22 AM, Alistair Francis wrote:
> From: Palmer Dabbelt <address@hidden>
> 
> We directly access physical memory while walking the page tables on
> RISC-V, but while doing so we were using cpu_ld*() which does not report
> bus errors.  This patch converts the page table walker over to use
> address_space_ld*(), which allows bus errors to be detected.
> 
> Signed-off-by: Palmer Dabbelt <address@hidden>
> Signed-off-by: Alistair Francis <address@hidden>
> ---
>  target/riscv/cpu_helper.c | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 87dd6a6ece..c82e7ed52b 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -169,7 +169,8 @@ static int get_physical_address(CPURISCVState *env, 
> hwaddr *physical,
>      /* NOTE: the env->pc value visible here will not be
>       * correct, but the value visible to the exception handler
>       * (riscv_cpu_do_interrupt) is correct */
> -
> +    MemTxResult res;
> +    MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
>      int mode = mmu_idx;
>  
>      if (mode == PRV_M && access_type != MMU_INST_FETCH) {
> @@ -256,11 +257,16 @@ restart:
>              1 << MMU_DATA_LOAD, PRV_S)) {
>              return TRANSLATE_PMP_FAIL;
>          }
> +
>  #if defined(TARGET_RISCV32)
> -        target_ulong pte = ldl_phys(cs->as, pte_addr);
> +        target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
>  #elif defined(TARGET_RISCV64)
> -        target_ulong pte = ldq_phys(cs->as, pte_addr);
> +        target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
>  #endif
> +        if (res != MEMTX_OK) {
> +            return TRANSLATE_FAIL;
> +        }
> +
>          hwaddr ppn = pte >> PTE_PPN_SHIFT;
>  
>          if (!(pte & PTE_V)) {
> 

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>