[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 05/21] aspeed/timer: Add support for control registe
From: |
Cédric Le Goater |
Subject: |
[Qemu-devel] [PATCH 05/21] aspeed/timer: Add support for control register 3 |
Date: |
Thu, 19 Sep 2019 07:49:46 +0200 |
The AST2500 timer has a third control register that is used to
implement a set-to-clear feature for the main control register.
This models the behaviour expected by the AST2500 while maintaining
the same behaviour for the AST2400.
The vmstate version is not increased yet because the structure is
modified again in the following patches.
Based on previous work from Joel Stanley.
Signed-off-by: Cédric Le Goater <address@hidden>
---
include/hw/timer/aspeed_timer.h | 1 +
hw/timer/aspeed_timer.c | 19 +++++++++++++++++++
2 files changed, 20 insertions(+)
diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h
index a791fee276f4..1e0288ebc49f 100644
--- a/include/hw/timer/aspeed_timer.h
+++ b/include/hw/timer/aspeed_timer.h
@@ -58,6 +58,7 @@ typedef struct AspeedTimerCtrlState {
uint32_t ctrl;
uint32_t ctrl2;
+ uint32_t ctrl3;
AspeedTimer timers[ASPEED_TIMER_NR_TIMERS];
AspeedSCUState *scu;
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
index c78bc1bd2d25..d70e78a0293e 100644
--- a/hw/timer/aspeed_timer.c
+++ b/hw/timer/aspeed_timer.c
@@ -498,6 +498,8 @@ static uint64_t aspeed_2500_timer_read(AspeedTimerCtrlState
*s, hwaddr offset)
switch (offset) {
case 0x38:
+ value = s->ctrl3 & BIT(0);
+ break;
case 0x3C:
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
@@ -511,9 +513,24 @@ static uint64_t
aspeed_2500_timer_read(AspeedTimerCtrlState *s, hwaddr offset)
static void aspeed_2500_timer_write(AspeedTimerCtrlState *s, hwaddr offset,
uint64_t value)
{
+ const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF);
+ uint8_t command;
+
switch (offset) {
case 0x38:
+ command = (value >> 1) & 0xFF;
+ if (command == 0xAE) {
+ s->ctrl3 = 0x1;
+ } else if (command == 0xEA) {
+ s->ctrl3 = 0x0;
+ }
+ break;
case 0x3C:
+ if (s->ctrl3 & BIT(0)) {
+ aspeed_timer_set_ctrl(s, s->ctrl & ~tv);
+ }
+ break;
+
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
__func__, offset);
@@ -574,6 +591,7 @@ static void aspeed_timer_reset(DeviceState *dev)
}
s->ctrl = 0;
s->ctrl2 = 0;
+ s->ctrl3 = 0;
}
static const VMStateDescription vmstate_aspeed_timer = {
@@ -597,6 +615,7 @@ static const VMStateDescription vmstate_aspeed_timer_state
= {
.fields = (VMStateField[]) {
VMSTATE_UINT32(ctrl, AspeedTimerCtrlState),
VMSTATE_UINT32(ctrl2, AspeedTimerCtrlState),
+ VMSTATE_UINT32(ctrl3, AspeedTimerCtrlState),
VMSTATE_STRUCT_ARRAY(timers, AspeedTimerCtrlState,
ASPEED_TIMER_NR_TIMERS, 1, vmstate_aspeed_timer,
AspeedTimer),
--
2.21.0
- [Qemu-devel] [PATCH 00/21] aspeed: Add support for the AST2600 SoC, Cédric Le Goater, 2019/09/19
- [Qemu-devel] [PATCH 01/21] aspeed/wdt: Check correct register for clock source, Cédric Le Goater, 2019/09/19
- [Qemu-devel] [PATCH 02/21] hw/sd/aspeed_sdhci: New device, Cédric Le Goater, 2019/09/19
- [Qemu-devel] [PATCH 03/21] hw: aspeed_scu: Add AST2600 support, Cédric Le Goater, 2019/09/19
- [Qemu-devel] [PATCH 04/21] aspeed/timer: Introduce an object class per SoC, Cédric Le Goater, 2019/09/19
- [Qemu-devel] [PATCH 05/21] aspeed/timer: Add support for control register 3,
Cédric Le Goater <=
- [Qemu-devel] [PATCH 06/21] aspeed/timer: Add AST2600 support, Cédric Le Goater, 2019/09/19
- [Qemu-devel] [PATCH 07/21] aspeed/timer: Add support for IRQ status register on the AST2600, Cédric Le Goater, 2019/09/19
- [Qemu-devel] [PATCH 08/21] aspeed/sdmc: Introduce an object class per SoC, Cédric Le Goater, 2019/09/19
- [Qemu-devel] [PATCH 09/21] aspeed/sdmc: Add AST2600 support, Cédric Le Goater, 2019/09/19
- [Qemu-devel] [PATCH 10/21] watchdog/aspeed: Introduce an object class per SoC, Cédric Le Goater, 2019/09/19
- [Qemu-devel] [PATCH 11/21] hw: wdt_aspeed: Add AST2600 support, Cédric Le Goater, 2019/09/19