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[Qemu-devel] [PULL 18/48] riscv: hw: Change create_fdt() to return void
From: |
Palmer Dabbelt |
Subject: |
[Qemu-devel] [PULL 18/48] riscv: hw: Change create_fdt() to return void |
Date: |
Wed, 18 Sep 2019 07:56:10 -0700 |
From: Bin Meng <address@hidden>
There is no need to return fdt at the end of create_fdt() because
it's already saved in s->fdt.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Chih-Min Chao <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_u.c | 11 ++++-------
hw/riscv/virt.c | 11 ++++-------
2 files changed, 8 insertions(+), 14 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e8acdd9b12..32d8cee335 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -67,7 +67,7 @@ static const struct MemmapEntry {
#define GEM_REVISION 0x10070109
-static void *create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
+static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
uint64_t mem_size, const char *cmdline)
{
void *fdt;
@@ -253,14 +253,11 @@ static void *create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
g_free(nodename);
-
- return fdt;
}
static void riscv_sifive_u_init(MachineState *machine)
{
const struct MemmapEntry *memmap = sifive_u_memmap;
- void *fdt;
SiFiveUState *s = g_new0(SiFiveUState, 1);
MemoryRegion *system_memory = get_system_memory();
@@ -281,7 +278,7 @@ static void riscv_sifive_u_init(MachineState *machine)
main_mem);
/* create device tree */
- fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
+ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
riscv_find_and_load_firmware(machine, BIOS_FILENAME,
memmap[SIFIVE_U_DRAM].base);
@@ -294,9 +291,9 @@ static void riscv_sifive_u_init(MachineState *machine)
hwaddr end = riscv_load_initrd(machine->initrd_filename,
machine->ram_size, kernel_entry,
&start);
- qemu_fdt_setprop_cell(fdt, "/chosen",
+ qemu_fdt_setprop_cell(s->fdt, "/chosen",
"linux,initrd-start", start);
- qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
+ qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
end);
}
}
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 090512be13..d36f5625ec 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -112,7 +112,7 @@ static void create_pcie_irq_map(void *fdt, char *nodename,
0x1800, 0, 0, 0x7);
}
-static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
+static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
uint64_t mem_size, const char *cmdline)
{
void *fdt;
@@ -316,8 +316,6 @@ static void *create_fdt(RISCVVirtState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
}
g_free(nodename);
-
- return fdt;
}
@@ -373,7 +371,6 @@ static void riscv_virt_board_init(MachineState *machine)
size_t plic_hart_config_len;
int i;
unsigned int smp_cpus = machine->smp.cpus;
- void *fdt;
/* Initialize SOC */
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
@@ -392,7 +389,7 @@ static void riscv_virt_board_init(MachineState *machine)
main_mem);
/* create device tree */
- fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
+ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
/* boot rom */
memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
@@ -411,9 +408,9 @@ static void riscv_virt_board_init(MachineState *machine)
hwaddr end = riscv_load_initrd(machine->initrd_filename,
machine->ram_size, kernel_entry,
&start);
- qemu_fdt_setprop_cell(fdt, "/chosen",
+ qemu_fdt_setprop_cell(s->fdt, "/chosen",
"linux,initrd-start", start);
- qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
+ qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
end);
}
}
--
2.21.0
- [Qemu-devel] [PULL 07/48] target/riscv: Create function to test if FP is enabled, (continued)
- [Qemu-devel] [PULL 07/48] target/riscv: Create function to test if FP is enabled, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 08/48] target/riscv: Update the Hypervisor CSRs to v0.4, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 09/48] riscv: rv32: Root page table address can be larger than 32-bit, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 11/48] riscv: Resolve full path of the given bios image, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 13/48] riscv: sifive_test: Add reset functionality, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 12/48] riscv: hmp: Add a command to show virtual memory mappings, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 17/48] riscv: hw: Remove not needed PLIC properties in device tree, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 16/48] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 14/48] riscv: hw: Remove duplicated "hw/hw.h" inclusion, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 15/48] riscv: hw: Remove superfluous "linux, phandle" property, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 18/48] riscv: hw: Change create_fdt() to return void,
Palmer Dabbelt <=
- [Qemu-devel] [PULL 19/48] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 20/48] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 22/48] riscv: sifive_u: Remove the unnecessary include of prci header, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 21/48] riscv: roms: Remove executable attribute of opensbi images, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 24/48] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 23/48] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 25/48] riscv: sifive_e: prci: Update the PRCI register block size, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 26/48] riscv: sifive_e: Drop sifive_mmio_emulate(), Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 27/48] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 30/48] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/18