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[Qemu-devel] [PULL 27/47] riscv: Add a sifive_cpu.h to include both E an
From: |
Palmer Dabbelt |
Subject: |
[Qemu-devel] [PULL 27/47] riscv: Add a sifive_cpu.h to include both E and U cpu type defines |
Date: |
Tue, 10 Sep 2019 12:04:53 -0700 |
From: Bin Meng <address@hidden>
Group SiFive E and U cpu type defines into one header file.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
include/hw/riscv/sifive_cpu.h | 31 +++++++++++++++++++++++++++++++
include/hw/riscv/sifive_e.h | 7 +------
include/hw/riscv/sifive_u.h | 7 +------
3 files changed, 33 insertions(+), 12 deletions(-)
create mode 100644 include/hw/riscv/sifive_cpu.h
diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h
new file mode 100644
index 0000000000..136799633a
--- /dev/null
+++ b/include/hw/riscv/sifive_cpu.h
@@ -0,0 +1,31 @@
+/*
+ * SiFive CPU types
+ *
+ * Copyright (c) 2017 SiFive, Inc.
+ * Copyright (c) 2019 Bin Meng <address@hidden>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_SIFIVE_CPU_H
+#define HW_SIFIVE_CPU_H
+
+#if defined(TARGET_RISCV32)
+#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31
+#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34
+#elif defined(TARGET_RISCV64)
+#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
+#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
+#endif
+
+#endif /* HW_SIFIVE_CPU_H */
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 9c868dd7f9..25ce7aa9d5 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -20,6 +20,7 @@
#define HW_SIFIVE_E_H
#include "hw/riscv/riscv_hart.h"
+#include "hw/riscv/sifive_cpu.h"
#include "hw/riscv/sifive_gpio.h"
#define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
@@ -84,10 +85,4 @@ enum {
#define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000
#define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000
-#if defined(TARGET_RISCV32)
-#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31
-#elif defined(TARGET_RISCV64)
-#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
-#endif
-
#endif
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index be021ce256..f25bad8f13 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -21,6 +21,7 @@
#include "hw/net/cadence_gem.h"
#include "hw/riscv/riscv_hart.h"
+#include "hw/riscv/sifive_cpu.h"
#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
#define RISCV_U_SOC(obj) \
@@ -78,10 +79,4 @@ enum {
#define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000
#define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000
-#if defined(TARGET_RISCV32)
-#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34
-#elif defined(TARGET_RISCV64)
-#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
-#endif
-
#endif
--
2.21.0
- [Qemu-devel] [PULL 17/47] riscv: hw: Remove not needed PLIC properties in device tree, (continued)
- [Qemu-devel] [PULL 17/47] riscv: hw: Remove not needed PLIC properties in device tree, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 16/47] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 18/47] riscv: hw: Change create_fdt() to return void, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 19/47] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 21/47] riscv: roms: Remove executable attribute of opensbi images, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 22/47] riscv: sifive_u: Remove the unnecessary include of prci header, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 20/47] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 24/47] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 23/47] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 25/47] riscv: sifive_e: prci: Update the PRCI register block size, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 27/47] riscv: Add a sifive_cpu.h to include both E and U cpu type defines,
Palmer Dabbelt <=
- [Qemu-devel] [PULL 26/47] riscv: sifive_e: Drop sifive_mmio_emulate(), Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 28/47] riscv: hart: Extract hart realize to a separate routine, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 30/47] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 32/47] riscv: sifive_u: Update PLIC hart topology configuration string, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 29/47] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 31/47] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 34/47] riscv: sifive_u: Generate hfclk and rtcclk nodes, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 35/47] riscv: sifive_u: Add PRCI block to the SoC, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 36/47] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 33/47] riscv: sifive: Implement PRCI model for FU540, Palmer Dabbelt, 2019/09/11