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[Qemu-devel] [PULL 09/47] riscv: rv32: Root page table address can be la
From: |
Palmer Dabbelt |
Subject: |
[Qemu-devel] [PULL 09/47] riscv: rv32: Root page table address can be larger than 32-bit |
Date: |
Tue, 10 Sep 2019 12:04:35 -0700 |
From: Bin Meng <address@hidden>
For RV32, the root page table's PPN has 22 bits hence its address
bits could be larger than the maximum bits that target_ulong is
able to represent. Use hwaddr instead.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu_helper.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 96373b67d8..87dd6a6ece 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -186,12 +186,12 @@ static int get_physical_address(CPURISCVState *env,
hwaddr *physical,
*prot = 0;
- target_ulong base;
+ hwaddr base;
int levels, ptidxbits, ptesize, vm, sum;
int mxr = get_field(env->mstatus, MSTATUS_MXR);
if (env->priv_ver >= PRIV_VERSION_1_10_0) {
- base = get_field(env->satp, SATP_PPN) << PGSHIFT;
+ base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
sum = get_field(env->mstatus, MSTATUS_SUM);
vm = get_field(env->satp, SATP_MODE);
switch (vm) {
@@ -211,7 +211,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
g_assert_not_reached();
}
} else {
- base = env->sptbr << PGSHIFT;
+ base = (hwaddr)(env->sptbr) << PGSHIFT;
sum = !get_field(env->mstatus, MSTATUS_PUM);
vm = get_field(env->mstatus, MSTATUS_VM);
switch (vm) {
@@ -249,7 +249,7 @@ restart:
((1 << ptidxbits) - 1);
/* check that physical address of PTE is legal */
- target_ulong pte_addr = base + idx * ptesize;
+ hwaddr pte_addr = base + idx * ptesize;
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
!pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
@@ -261,7 +261,7 @@ restart:
#elif defined(TARGET_RISCV64)
target_ulong pte = ldq_phys(cs->as, pte_addr);
#endif
- target_ulong ppn = pte >> PTE_PPN_SHIFT;
+ hwaddr ppn = pte >> PTE_PPN_SHIFT;
if (!(pte & PTE_V)) {
/* Invalid PTE */
--
2.21.0
- [Qemu-devel] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 01/47] riscv: sifive_u: Add support for loading initrd, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 02/47] riscv: sivive_u: Add dummy serial clock and aliases entry for uart, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 03/47] riscv: sifive_u: Fix clock-names property for ethernet node, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 04/47] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 05/47] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 06/47] riscv: plic: Remove unused interrupt functions, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 08/47] target/riscv: Update the Hypervisor CSRs to v0.4, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 07/47] target/riscv: Create function to test if FP is enabled, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 09/47] riscv: rv32: Root page table address can be larger than 32-bit,
Palmer Dabbelt <=
- [Qemu-devel] [PULL 10/47] riscv: Add a helper routine for finding firmware, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 11/47] riscv: Resolve full path of the given bios image, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 13/47] riscv: sifive_test: Add reset functionality, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 12/47] riscv: hmp: Add a command to show virtual memory mappings, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 14/47] riscv: hw: Remove duplicated "hw/hw.h" inclusion, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 15/47] riscv: hw: Remove superfluous "linux, phandle" property, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 17/47] riscv: hw: Remove not needed PLIC properties in device tree, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 16/47] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 18/47] riscv: hw: Change create_fdt() to return void, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 19/47] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead, Palmer Dabbelt, 2019/09/11