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[Qemu-devel] [RFC 2 PATCH 05/16] hw/i386: Simplify topology Offset/width
From: |
Moger, Babu |
Subject: |
[Qemu-devel] [RFC 2 PATCH 05/16] hw/i386: Simplify topology Offset/width Calculation |
Date: |
Fri, 6 Sep 2019 19:12:11 +0000 |
Some parameters are unnecessarily passed for offset/width
calculation. Remove those parameters from function prototypes.
No functional change.
Signed-off-by: Babu Moger <address@hidden>
---
include/hw/i386/topology.h | 45 ++++++++++++++++++--------------------------
target/i386/cpu.c | 12 ++++--------
2 files changed, 22 insertions(+), 35 deletions(-)
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index 906017e8e3..fb10863a66 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -73,46 +73,37 @@ static unsigned apicid_bitwidth_for_count(unsigned count)
/* Bit width of the SMT_ID (thread ID) field on the APIC ID
*/
-static inline unsigned apicid_smt_width(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_smt_width(unsigned nr_threads)
{
return apicid_bitwidth_for_count(nr_threads);
}
/* Bit width of the Core_ID field
*/
-static inline unsigned apicid_core_width(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_core_width(unsigned nr_cores)
{
return apicid_bitwidth_for_count(nr_cores);
}
/* Bit width of the Die_ID field */
-static inline unsigned apicid_die_width(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_die_width(unsigned nr_dies)
{
return apicid_bitwidth_for_count(nr_dies);
}
/* Bit offset of the Core_ID field
*/
-static inline unsigned apicid_core_offset(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_core_offset(unsigned nr_threads)
{
- return apicid_smt_width(nr_dies, nr_cores, nr_threads);
+ return apicid_smt_width(nr_threads);
}
/* Bit offset of the Die_ID field */
-static inline unsigned apicid_die_offset(unsigned nr_dies,
- unsigned nr_cores,
- unsigned nr_threads)
+static inline unsigned apicid_die_offset(unsigned nr_cores,
+ unsigned nr_threads)
{
- return apicid_core_offset(nr_dies, nr_cores, nr_threads) +
- apicid_core_width(nr_dies, nr_cores, nr_threads);
+ return apicid_core_offset(nr_threads) +
+ apicid_core_width(nr_cores);
}
/* Bit offset of the Pkg_ID (socket ID) field
@@ -121,8 +112,8 @@ static inline unsigned apicid_pkg_offset(unsigned nr_dies,
unsigned nr_cores,
unsigned nr_threads)
{
- return apicid_die_offset(nr_dies, nr_cores, nr_threads) +
- apicid_die_width(nr_dies, nr_cores, nr_threads);
+ return apicid_die_offset(nr_cores, nr_threads) +
+ apicid_die_width(nr_dies);
}
/* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
@@ -137,8 +128,8 @@ static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo
*topo_info,
unsigned nr_threads = topo_info->nr_threads;
return (topo_ids->pkg_id << apicid_pkg_offset(nr_dies, nr_cores,
nr_threads)) |
- (topo_ids->die_id << apicid_die_offset(nr_dies, nr_cores,
nr_threads)) |
- (topo_ids->core_id << apicid_core_offset(nr_dies, nr_cores,
nr_threads)) |
+ (topo_ids->die_id << apicid_die_offset(nr_cores, nr_threads)) |
+ (topo_ids->core_id << apicid_core_offset(nr_threads)) |
topo_ids->smt_id;
}
@@ -171,13 +162,13 @@ static inline void x86_topo_ids_from_apicid(apic_id_t
apicid,
unsigned nr_threads = topo_info->nr_threads;
topo_ids->smt_id = apicid &
- ~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threads));
+ ~(0xFFFFFFFFUL << apicid_smt_width(nr_threads));
topo_ids->core_id =
- (apicid >> apicid_core_offset(nr_dies, nr_cores, nr_threads)) &
- ~(0xFFFFFFFFUL << apicid_core_width(nr_dies, nr_cores,
nr_threads));
+ (apicid >> apicid_core_offset(nr_threads)) &
+ ~(0xFFFFFFFFUL << apicid_core_width(nr_cores));
topo_ids->die_id =
- (apicid >> apicid_die_offset(nr_dies, nr_cores, nr_threads)) &
- ~(0xFFFFFFFFUL << apicid_die_width(nr_dies, nr_cores, nr_threads));
+ (apicid >> apicid_die_offset(nr_cores, nr_threads)) &
+ ~(0xFFFFFFFFUL << apicid_die_width(nr_dies));
topo_ids->pkg_id = apicid >> apicid_pkg_offset(nr_dies, nr_cores,
nr_threads);
}
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 19751e37a7..6d7f9b6b8b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4260,8 +4260,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
eax, ebx, ecx, edx);
break;
case 3: /* L3 cache info */
- die_offset = apicid_die_offset(env->nr_dies,
- cs->nr_cores, cs->nr_threads);
+ die_offset = apicid_die_offset(cs->nr_cores, cs->nr_threads);
if (cpu->enable_l3_cache) {
encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
(1 << die_offset), cs->nr_cores,
@@ -4346,8 +4345,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
switch (count) {
case 0:
- *eax = apicid_core_offset(env->nr_dies,
- cs->nr_cores, cs->nr_threads);
+ *eax = apicid_core_offset(cs->nr_threads);
*ebx = cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
break;
@@ -4377,14 +4375,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
*edx = cpu->apic_id;
switch (count) {
case 0:
- *eax = apicid_core_offset(env->nr_dies, cs->nr_cores,
- cs->nr_threads);
+ *eax = apicid_core_offset(cs->nr_threads);
*ebx = cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
break;
case 1:
- *eax = apicid_die_offset(env->nr_dies, cs->nr_cores,
- cs->nr_threads);
+ *eax = apicid_die_offset(cs->nr_cores, cs->nr_threads);
*ebx = cs->nr_cores * cs->nr_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
break;
- [Qemu-devel] [RFC 2 PATCH 00/16] APIC ID fixes for AMD EPYC CPU models, Moger, Babu, 2019/09/06
- [Qemu-devel] [RFC 2 PATCH 01/16] numa: Split the numa functionality, Moger, Babu, 2019/09/06
- [Qemu-devel] [RFC 2 PATCH 02/16] hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs, Moger, Babu, 2019/09/06
- [Qemu-devel] [RFC 2 PATCH 03/16] hw/i386: Introduce X86CPUTopoInfo to contain topology info, Moger, Babu, 2019/09/06
- [Qemu-devel] [RFC 2 PATCH 04/16] machine: Add SMP Sockets in CpuTopology, Moger, Babu, 2019/09/06
- [Qemu-devel] [RFC 2 PATCH 05/16] hw/i386: Simplify topology Offset/width Calculation,
Moger, Babu <=
- [Qemu-devel] [RFC 2 PATCH 06/16] hw/core: Add core complex id in X86CPU topology, Moger, Babu, 2019/09/06
- [Qemu-devel] [RFC 2 PATCH 07/16] hw/386: Add new epyc mode topology decoding functions, Moger, Babu, 2019/09/06
- [Qemu-devel] [RFC 2 PATCH 08/16] i386: Cleanup and use the new epyc mode topology functions, Moger, Babu, 2019/09/06
- [Qemu-devel] [RFC 2 PATCH 09/16] hw/i386: Introduce initialize_topo_info function, Moger, Babu, 2019/09/06
- [Qemu-devel] [RFC 2 PATCH 10/16] hw/i386: Introduce apicid_from_cpu_idx in PCMachineState, Moger, Babu, 2019/09/06
- [Qemu-devel] [RFC 2 PATCH 11/16] Introduce-topo_ids_from_apicid-handler, Moger, Babu, 2019/09/06