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[Qemu-devel] [PATCH v8 22/32] riscv: sifive_u: Generate hfclk and rtcclk
From: |
Bin Meng |
Subject: |
[Qemu-devel] [PATCH v8 22/32] riscv: sifive_u: Generate hfclk and rtcclk nodes |
Date: |
Fri, 6 Sep 2019 09:20:09 -0700 |
To keep in sync with Linux kernel device tree, generate hfclk and
rtcclk nodes in the device tree, to be referenced by PRCI node.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_u.c | 23 +++++++++++++++++++++++
include/hw/riscv/sifive_u.h | 2 ++
2 files changed, 25 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 713c451..3ee6fcb 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -79,6 +79,7 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
char ethclk_names[] = "pclk\0hclk\0tx_clk";
uint32_t plic_phandle, ethclk_phandle, phandle = 1;
uint32_t uartclk_phandle;
+ uint32_t hfclk_phandle, rtcclk_phandle;
fdt = s->fdt = create_device_tree(&s->fdt_size);
if (!fdt) {
@@ -97,6 +98,28 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
+ hfclk_phandle = phandle++;
+ nodename = g_strdup_printf("/hfclk");
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
+ qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+ SIFIVE_U_HFCLK_FREQ);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
+ qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
+ g_free(nodename);
+
+ rtcclk_phandle = phandle++;
+ nodename = g_strdup_printf("/rtcclk");
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
+ qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+ SIFIVE_U_RTCCLK_FREQ);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
+ qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
+ g_free(nodename);
+
nodename = g_strdup_printf("/memory@%lx",
(long)memmap[SIFIVE_U_DRAM].base);
qemu_fdt_add_subnode(fdt, nodename);
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 6b2b5b6..2441814 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -69,6 +69,8 @@ enum {
enum {
SIFIVE_U_CLOCK_FREQ = 1000000000,
+ SIFIVE_U_HFCLK_FREQ = 33333333,
+ SIFIVE_U_RTCCLK_FREQ = 1000000,
SIFIVE_U_GEM_CLOCK_FREQ = 125000000
};
--
2.7.4
- [Qemu-devel] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, (continued)
- [Qemu-devel] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/09/06
- Re: [Qemu-devel] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/13
- Re: [Qemu-devel] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/09/13
- Re: [Qemu-devel] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/14
- Re: [Qemu-devel] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/09/15
- Re: [Qemu-devel] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/15
- Re: [Qemu-devel] [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Jonathan Behrens, 2019/09/15
- Re: [Qemu-devel] [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/15
- Re: [Qemu-devel] [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/09/16
- Re: [Qemu-devel] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2, Alistair Francis, 2019/09/16
[Qemu-devel] [PATCH v8 22/32] riscv: sifive_u: Generate hfclk and rtcclk nodes,
Bin Meng <=
[Qemu-devel] [PATCH v8 17/32] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Bin Meng, 2019/09/06
[Qemu-devel] [PATCH v8 20/32] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/09/06
[Qemu-devel] [PATCH v8 21/32] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/09/06
[Qemu-devel] [PATCH v8 24/32] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Bin Meng, 2019/09/06
[Qemu-devel] [PATCH v8 19/32] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/09/06
[Qemu-devel] [PATCH v8 26/32] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/09/06
[Qemu-devel] [PATCH v8 25/32] riscv: sifive_u: Update UART base addresses and IRQs, Bin Meng, 2019/09/06
[Qemu-devel] [PATCH v8 23/32] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/09/06
[Qemu-devel] [PATCH v8 29/32] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/09/06