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[Qemu-devel] [PATCH v4 31/69] target/arm: Diagnose base == pc for LDM/ST
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v4 31/69] target/arm: Diagnose base == pc for LDM/STM |
Date: |
Wed, 4 Sep 2019 12:30:21 -0700 |
We have been using store_reg and not store_reg_for_load when writing
back a loaded value into the base register. At first glance this is
incorrect when base == pc, however that case is UNPREDICTABLE.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index b623dbcd48..d0fc916ff9 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9863,7 +9863,7 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a,
int min_n)
list = a->list;
n = ctpop16(list);
- if (n < min_n) {
+ if (n < min_n || a->rn == 15) {
unallocated_encoding(s);
return true;
}
@@ -9943,7 +9943,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a,
int min_n)
list = a->list;
n = ctpop16(list);
- if (n < min_n) {
+ if (n < min_n || a->rn == 15) {
unallocated_encoding(s);
return true;
}
@@ -9983,6 +9983,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a,
int min_n)
op_addr_block_post(s, a, addr, n);
if (loaded_base) {
+ /* Note that we reject base == pc above. */
store_reg(s, a->rn, loaded_var);
}
--
2.17.1
- [Qemu-devel] [PATCH v4 19/69] target/arm: Convert T32 ADDW/SUBW, (continued)
- [Qemu-devel] [PATCH v4 19/69] target/arm: Convert T32 ADDW/SUBW, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 17/69] target/arm: Convert ERET, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 18/69] target/arm: Convert the rest of A32 Miscelaneous instructions, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 22/69] target/arm: Diagnose UNPREDICTABLE ldrex/strex cases, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 21/69] target/arm: Convert Synchronization primitives, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 23/69] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 24/69] target/arm: Convert Parallel addition and subtraction, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 27/69] target/arm: Convert MOVW, MOVT, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 29/69] target/arm: Diagnose writeback register in list for LDM for v7, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 20/69] target/arm: Convert load/store (register, immediate, literal), Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 31/69] target/arm: Diagnose base == pc for LDM/STM,
Richard Henderson <=
- [Qemu-devel] [PATCH v4 30/69] target/arm: Diagnose too few registers in list for LDM/STM, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 26/69] target/arm: Convert Signed multiply, signed and unsigned divide, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 28/69] target/arm: Convert LDM, STM, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 33/69] target/arm: Convert SVC, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 25/69] target/arm: Convert packing, unpacking, saturation, and reversal, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 32/69] target/arm: Convert B, BL, BLX (immediate), Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 37/69] target/arm: Convert SETEND, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 36/69] target/arm: Convert CPS (privileged), Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 34/69] target/arm: Convert RFE and SRS, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 35/69] target/arm: Convert Clear-Exclusive, Barriers, Richard Henderson, 2019/09/04