[Qemu-devel] [Bug 1841990] Re: instruction 'denbcdq' misbehaving

[Philippe Mathieu-Daudé]

This seems related to this change:

commit ef96e3ae9698d6726a8113f448c82985a9f31ff5
Author: Mark Cave-Ayland <address@hidden>
Date:   Wed Jan 2 09:14:22 2019 +0000

    target/ppc: move FP and VMX registers into aligned vsr register array
    
    The VSX register array is a block of 64 128-bit registers where the first 32
    registers consist of the existing 64-bit FP registers extended to 128-bit
    using new VSR registers, and the last 32 registers are the VMX 128-bit
    registers as show below:
    
                64-bit               64-bit
        +--------------------+--------------------+
        |        FP0         |                    |  VSR0
        +--------------------+--------------------+
        |        FP1         |                    |  VSR1
        +--------------------+--------------------+
        |        ...         |        ...         |  ...
        +--------------------+--------------------+
        |        FP30        |                    |  VSR30
        +--------------------+--------------------+
        |        FP31        |                    |  VSR31
        +--------------------+--------------------+
        |                  VMX0                   |  VSR32
        +-----------------------------------------+
        |                  VMX1                   |  VSR33
        +-----------------------------------------+
        |                  ...                    |  ...
        +-----------------------------------------+
        |                  VMX30                  |  VSR62
        +-----------------------------------------+
        |                  VMX31                  |  VSR63
        +-----------------------------------------+
    
    In order to allow for future conversion of VSX instructions to use TCG 
vector
    operations, recreate the same layout using an aligned version of the 
existing
    vsr register array.
    
    Since the old fpr and avr register arrays are removed, the existing callers
    must also be updated to use the correct offset in the vsr register array. 
This
    also includes switching the relevant VMState fields over to using subarrays
    to make sure that migration is preserved.

@@ -1055,11 +1053,10 @@ struct CPUPPCState {
-    /* VSX registers */
-    uint64_t vsr[32];
+    /* VSX registers (including FP and AVR) */
+    ppc_vsr_t vsr[64] QEMU_ALIGNED(16);

The denbcdq helper is:

#define DFP_HELPER_ENBCD(op, size)                                           \
void helper_##op(CPUPPCState *env, uint64_t *t, uint64_t *b, uint32_t s)     \
{                                                                            \
[...]
    if ((size) == 64) {                                                      \
        t[0] = dfp.t64[0];                                                   \
    } else if ((size) == 128) {                                              \
        t[0] = dfp.t64[HI_IDX];                                              \
        t[1] = dfp.t64[LO_IDX];                                              \
    }                                                                        \
}

t[1] doesn't point to the proper vsr register anymore.

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https://bugs.launchpad.net/bugs/1841990

Title:
  instruction 'denbcdq' misbehaving

Status in QEMU:
  New

Bug description:
  Instruction 'denbcdq' appears to have no effect.  Test case attached.

  On ppc64le native:
  --
  gcc -g -O -mcpu=power9 bcdcfsq.c test-denbcdq.c -o test-denbcdq
  $ ./test-denbcdq
  0x00000000000000000000000000000000
  0x0000000000000000000000000000000c
  0x22080000000000000000000000000000
  $ ./test-denbcdq 1
  0x00000000000000000000000000000001
  0x0000000000000000000000000000001c
  0x22080000000000000000000000000001
  $ ./test-denbcdq $(seq 0 99)
  0x00000000000000000000000000000064
  0x0000000000000000000000000000100c
  0x22080000000000000000000000000080
  --

  With "qemu-ppc64le -cpu power9"
  --
  $ qemu-ppc64le -cpu power9 -L [...] ./test-denbcdq
  0x00000000000000000000000000000000
  0x0000000000000000000000000000000c
  0x0000000000000000000000000000000c
  $ qemu-ppc64le -cpu power9 -L [...] ./test-denbcdq 1
  0x00000000000000000000000000000001
  0x0000000000000000000000000000001c
  0x0000000000000000000000000000001c
  $ qemu-ppc64le -cpu power9 -L [...] ./test-denbcdq $(seq 100)
  0x00000000000000000000000000000064
  0x0000000000000000000000000000100c
  0x0000000000000000000000000000100c
  --

  I started looking at the code, but I got confused rather quickly.
  Could be related to endianness? I think denbcdq arrived on the scene
  before little-endian was a big deal.  Maybe something to do with
  utilizing implicit floating-point register pairs...  I don't think the
  right data is getting to helper_denbcdq, which would point back to the
  gen_fprp_ptr uses in dfp-impl.inc.c (GEN_DFP_T_FPR_I32_Rc).  (Maybe?)

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