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[Qemu-devel] [PATCH v1 04/28] target/riscv: Fix CSR perm checking for HS
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From: |
Alistair Francis |
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Subject: |
[Qemu-devel] [PATCH v1 04/28] target/riscv: Fix CSR perm checking for HS mode |
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Date: |
Fri, 23 Aug 2019 16:38:00 -0700 |
Update the CSR permission checking to work correctly when we are in
HS-mode.
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/csr.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f767ad24be..471f23a1d0 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -799,9 +799,15 @@ int riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
/* check privileges and return -1 if check fails */
#if !defined(CONFIG_USER_ONLY)
- int csr_priv = get_field(csrno, 0x300);
+ int csr_priv = env->priv;
int read_only = get_field(csrno, 0xC00) == 3;
- if ((write_mask && read_only) || (env->priv < csr_priv)) {
+
+ if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
+ /* Plus 1 as we are in HS mode */
+ csr_priv++;
+ }
+
+ if ((write_mask && read_only) || (csr_priv < get_field(csrno, 0x300))) {
return -1;
}
#endif
--
2.22.0
- [Qemu-devel] [PATCH v1 00/28] Add RISC-V Hypervisor Extension v0.4, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 02/28] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 01/28] target/riscv: Add the Hypervisor extension, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 04/28] target/riscv: Fix CSR perm checking for HS mode,
Alistair Francis <=
- [Qemu-devel] [PATCH v1 03/28] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 06/28] target/riscv: Print priv and virt in disas log, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 08/28] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 07/28] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 09/28] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 12/28] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 11/28] target/riscv: Add background register swapping function, Alistair Francis, 2019/08/23