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[Qemu-devel] [PATCH v5 08/30] riscv: sifive_u: Remove the unnecessary in
From: |
Bin Meng |
Subject: |
[Qemu-devel] [PATCH v5 08/30] riscv: sifive_u: Remove the unnecessary include of prci header |
Date: |
Thu, 22 Aug 2019 22:10:47 -0700 |
sifive_u machine does not use PRCI as of today. Remove the prci
header inclusion.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_u.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e22803b..3f58f61 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -39,7 +39,6 @@
#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_uart.h"
-#include "hw/riscv/sifive_prci.h"
#include "hw/riscv/sifive_u.h"
#include "hw/riscv/boot.h"
#include "chardev/char.h"
--
2.7.4
- [Qemu-devel] [PATCH v5 01/30] riscv: hw: Remove superfluous "linux, phandle" property, (continued)
- [Qemu-devel] [PATCH v5 01/30] riscv: hw: Remove superfluous "linux, phandle" property, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 03/30] riscv: hw: Remove not needed PLIC properties in device tree, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 04/30] riscv: hw: Change create_fdt() to return void, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 07/30] riscv: roms: Remove executable attribute of opensbi images, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 08/30] riscv: sifive_u: Remove the unnecessary include of prci header,
Bin Meng <=
- [Qemu-devel] [PATCH v5 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 11/30] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 14/30] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 17/30] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 18/30] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 16/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/23