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[Qemu-devel] [PATCH 14/26] target/mips: Clean up handling of CP0 registe
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH 14/26] target/mips: Clean up handling of CP0 register 17 |
Date: |
Thu, 22 Aug 2019 13:35:38 +0200 |
From: Aleksandar Markovic <address@hidden>
Clean up handling of CP0 register 17.
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7878fcb..51c8d29 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6671,12 +6671,12 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_LLAddr),
ctx->CP0_LLAddr_shift);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mfhc0_maar(arg, cpu_env);
register_name = "MAAR";
@@ -6772,7 +6772,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
/*
* LLAddr is read-only (the only exception is bit 0 if LLB is
* supported); the CP0_LLAddr_rw_bitmask does not seem to be
@@ -6781,7 +6781,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
*/
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mthc0_maar(cpu_env, arg);
register_name = "MAAR";
@@ -7332,16 +7332,16 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_helper_mfc0_lladdr(arg, cpu_env);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mfc0_maar(arg, cpu_env);
register_name = "MAAR";
break;
- case 2:
+ case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
register_name = "MAARI";
@@ -8071,16 +8071,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_helper_mtc0_lladdr(cpu_env, arg);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maar(cpu_env, arg);
register_name = "MAAR";
break;
- case 2:
+ case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maari(cpu_env, arg);
register_name = "MAARI";
@@ -8816,16 +8816,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_helper_dmfc0_lladdr(arg, cpu_env);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_dmfc0_maar(arg, cpu_env);
register_name = "MAAR";
break;
- case 2:
+ case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
register_name = "MAARI";
@@ -9537,16 +9537,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_helper_mtc0_lladdr(cpu_env, arg);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maar(cpu_env, arg);
register_name = "MAAR";
break;
- case 2:
+ case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maari(cpu_env, arg);
register_name = "MAARI";
--
2.7.4
- [Qemu-devel] [PATCH 00/26] Clean up handling of configuration register CP0, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 10/26] target/mips: Clean up handling of CP0 register 11, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 09/26] target/mips: Clean up handling of CP0 register 10, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 01/26] target/mips: Clean up handling of CP0 register 0, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 07/26] target/mips: Clean up handling of CP0 register 8, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 04/26] target/mips: Clean up handling of CP0 register 5, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 02/26] target/mips: Clean up handling of CP0 register 1, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 06/26] target/mips: Clean up handling of CP0 register 7, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 08/26] target/mips: Clean up handling of CP0 register 9, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 16/26] target/mips: Clean up handling of CP0 register 19, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 14/26] target/mips: Clean up handling of CP0 register 17,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH 13/26] target/mips: Clean up handling of CP0 register 16, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 12/26] target/mips: Clean up handling of CP0 register 15, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 03/26] target/mips: Clean up handling of CP0 register 2, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 15/26] target/mips: Clean up handling of CP0 register 18, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 11/26] target/mips: Clean up handling of CP0 register 12, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 05/26] target/mips: Clean up handling of CP0 register 6, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 19/26] target/mips: Clean up handling of CP0 register 24, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 22/26] target/mips: Clean up handling of CP0 register 27, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 25/26] target/mips: Clean up handling of CP0 register 30, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 17/26] target/mips: Clean up handling of CP0 register 20, Aleksandar Markovic, 2019/08/22