qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] [EXTERNAL][PATCH v8 03/37] target/mips: Amend CP0 Memor


From: Aleksandar Rikalo
Subject: Re: [Qemu-devel] [EXTERNAL][PATCH v8 03/37] target/mips: Amend CP0 MemoryMapID register implementation
Date: Mon, 19 Aug 2019 14:39:07 +0000

> From: Aleksandar Markovic <address@hidden>
> Sent: Monday, August 19, 2019 2:07 PM
> To: address@hidden <address@hidden>
> Cc: address@hidden <address@hidden>; Aleksandar Markovic <address@hidden>; 
> Aleksandar Rikalo <address@hidden>
> Subject: [EXTERNAL][PATCH v8 03/37] target/mips: Amend CP0 MemoryMapID 
> register implementation
>
> From: Yongbok Kim <address@hidden>
>
> Add migration support and fix preprocessor constant name for
> MemoryMapID register.
>
> Signed-off-by: Yongbok Kim <address@hidden>
> Signed-off-by: Aleksandar Markovic <address@hidden>
> ---
>  target/mips/cpu.h     | 2 +-
>  target/mips/machine.c | 7 +++++--
>  2 files changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 6406ba8..eda8350 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -290,7 +290,7 @@ typedef struct mips_def_t mips_def_t;
>  #define CP0_REG04__CONTEXT         0
>  #define CP0_REG04__USERLOCAL       2
>  #define CP0_REG04__DBGCONTEXTID    4
> -#define CP0_REG00__MMID            5
> +#define CP0_REG04__MEMORYMAPID     5
>  /* CP0 Register 05 */
>  #define CP0_REG05__PAGEMASK        0
>  #define CP0_REG05__PAGEGRAIN       1
> diff --git a/target/mips/machine.c b/target/mips/machine.c
> index c3e52f8..e23b767 100644
> --- a/target/mips/machine.c
> +++ b/target/mips/machine.c
> @@ -137,6 +137,7 @@ static int get_tlb(QEMUFile *f, void *pv, size_t size,
>      qemu_get_betls(f, &v->VPN);
>      qemu_get_be32s(f, &v->PageMask);
>      qemu_get_be16s(f, &v->ASID);
> +    qemu_get_be32s(f, &v->MMID);
>      qemu_get_be16s(f, &flags);
>      v->G = (flags >> 10) & 1;
>      v->C0 = (flags >> 7) & 3;
> @@ -162,6 +163,7 @@ static int put_tlb(QEMUFile *f, void *pv, size_t size,
>      r4k_tlb_t *v = pv;
>
>      uint16_t asid = v->ASID;
> +    uint32_t mmid = v->MMID;
>      uint16_t flags = ((v->EHINV << 15) |
>                        (v->RI1 << 14) |
>                        (v->RI0 << 13) |
> @@ -178,6 +180,7 @@ static int put_tlb(QEMUFile *f, void *pv, size_t size,
>      qemu_put_betls(f, &v->VPN);
>      qemu_put_be32s(f, &v->PageMask);
>      qemu_put_be16s(f, &asid);
> +    qemu_put_be32s(f, &mmid);
>      qemu_put_be16s(f, &flags);
>      qemu_put_be64s(f, &v->PFN[0]);
>      qemu_put_be64s(f, &v->PFN[1]);
> @@ -199,8 +202,8 @@ const VMStateInfo vmstate_info_tlb = {
>
>  const VMStateDescription vmstate_tlb = {
>      .name = "cpu/tlb",
> -    .version_id = 2,
> -    .minimum_version_id = 2,
> +    .version_id = 3,
> +    .minimum_version_id = 3,
>      .fields = (VMStateField[]) {
>          VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
>          VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),
> --
> 2.7.4
>

Reviewed-by: Aleksandar Rikalo <address@hidden>



reply via email to

[Prev in Thread] Current Thread [Next in Thread]