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Re: [Qemu-devel] [PATCH v3 4/7] target/riscv: Update the Hypervisor CSRs
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From: |
Bin Meng |
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Subject: |
Re: [Qemu-devel] [PATCH v3 4/7] target/riscv: Update the Hypervisor CSRs to v0.4 |
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Date: |
Fri, 16 Aug 2019 21:59:15 +0800 |
On Fri, Aug 16, 2019 at 5:41 AM Alistair Francis
<address@hidden> wrote:
>
> Update the Hypervisor CSR addresses to match the v0.4 spec.
>
> Signed-off-by: Alistair Francis <address@hidden>
> Reviewed-by: Chih-Min Chao <address@hidden>
> ---
> target/riscv/cpu_bits.h | 35 ++++++++++++++++++-----------------
> 1 file changed, 18 insertions(+), 17 deletions(-)
>
Reviewed-by: Bin Meng <address@hidden>
- [Qemu-devel] [PATCH v3 0/7] RISC-V: Hypervisor prep work part 2, Alistair Francis, 2019/08/15
- [Qemu-devel] [PATCH v3 1/7] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/08/15
- [Qemu-devel] [PATCH v3 3/7] target/riscv: Create function to test if FP is enabled, Alistair Francis, 2019/08/15
- [Qemu-devel] [PATCH v3 2/7] riscv: plic: Remove unused interrupt functions, Alistair Francis, 2019/08/15
- [Qemu-devel] [PATCH v3 4/7] target/riscv: Update the Hypervisor CSRs to v0.4, Alistair Francis, 2019/08/15
- Re: [Qemu-devel] [PATCH v3 4/7] target/riscv: Update the Hypervisor CSRs to v0.4,
Bin Meng <=
- [Qemu-devel] [PATCH v3 5/7] target/riscv: Use both register name and ABI name, Alistair Francis, 2019/08/15
- [Qemu-devel] [PATCH v3 6/7] target/riscv: Fix mstatus dirty mask, Alistair Francis, 2019/08/15
- [Qemu-devel] [PATCH v3 7/7] target/riscv: Convert mip to target_ulong, Alistair Francis, 2019/08/15
- Re: [Qemu-devel] [PATCH v3 0/7] RISC-V: Hypervisor prep work part 2, no-reply, 2019/08/15