Re: [Qemu-devel] [PATCH for 4.2 v5 09/12] target/mips: Style improvements in internal.h

[Philippe Mathieu-Daudé]

On 8/1/19 6:45 PM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <address@hidden>
> 
> Fixes mostly errors and warings reported by 'checkpatch.pl -f'.

"warnings"

> 
> Signed-off-by: Aleksandar Markovic <address@hidden>

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>

> ---
>  target/mips/internal.h | 57 
> +++++++++++++++++++++++++++++++-------------------
>  1 file changed, 35 insertions(+), 22 deletions(-)
> 
> diff --git a/target/mips/internal.h b/target/mips/internal.h
> index d9216fb..836de7a 100644
> --- a/target/mips/internal.h
> +++ b/target/mips/internal.h
> @@ -1,4 +1,5 @@
> -/* mips internal definitions and helpers
> +/*
> + * MIPS internal definitions and helpers
>   *
>   * This work is licensed under the terms of the GNU GPL, version 2 or later.
>   * See the COPYING file in the top-level directory.
> @@ -8,8 +9,10 @@
>  #define MIPS_INTERNAL_H
>  
>  
> -/* MMU types, the first four entries have the same layout as the
> -   CP0C0_MT field.  */
> +/*
> + * MMU types, the first four entries have the same layout as the
> + * CP0C0_MT field.
> + */
>  enum mips_mmu_types {
>      MMU_TYPE_NONE,
>      MMU_TYPE_R4000,
> @@ -159,9 +162,11 @@ static inline bool 
> cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
>          !(env->CP0_Status & (1 << CP0St_EXL)) &&
>          !(env->CP0_Status & (1 << CP0St_ERL)) &&
>          !(env->hflags & MIPS_HFLAG_DM) &&
> -        /* Note that the TCStatus IXMT field is initialized to zero,
> -           and only MT capable cores can set it to one. So we don't
> -           need to check for MT capabilities here.  */
> +        /*
> +         * Note that the TCStatus IXMT field is initialized to zero,
> +         * and only MT capable cores can set it to one. So we don't
> +         * need to check for MT capabilities here.
> +         */
>          !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
>  }
>  
> @@ -176,14 +181,18 @@ static inline bool 
> cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
>      status = env->CP0_Status & CP0Ca_IP_mask;
>  
>      if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
> -        /* A MIPS configured with a vectorizing external interrupt controller
> -           will feed a vector into the Cause pending lines. The core treats
> -           the status lines as a vector level, not as indiviual masks.  */
> +        /*
> +         * A MIPS configured with a vectorizing external interrupt controller
> +         * will feed a vector into the Cause pending lines. The core treats
> +         * the status lines as a vector level, not as indiviual masks.
> +         */
>          r = pending > status;
>      } else {
> -        /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
> -           treats the pending lines as individual interrupt lines, the status
> -           lines are individual masks.  */
> +        /*
> +         * A MIPS configured with compatibility or VInt (Vectored Interrupts)
> +         * treats the pending lines as individual interrupt lines, the status
> +         * lines are individual masks.
> +         */
>          r = (pending & status) != 0;
>      }
>      return r;
> @@ -268,12 +277,14 @@ static inline int mips_vpe_active(CPUMIPSState *env)
>          active = 0;
>      }
>  
> -    /* Now verify that there are active thread contexts in the VPE.
> -
> -       This assumes the CPU model will internally reschedule threads
> -       if the active one goes to sleep. If there are no threads available
> -       the active one will be in a sleeping state, and we can turn off
> -       the entire VPE.  */
> +    /*
> +     * Now verify that there are active thread contexts in the VPE.
> +     *
> +     * This assumes the CPU model will internally reschedule threads
> +     * if the active one goes to sleep. If there are no threads available
> +     * the active one will be in a sleeping state, and we can turn off
> +     * the entire VPE.
> +     */
>      if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
>          /* TC is not activated.  */
>          active = 0;
> @@ -396,10 +407,12 @@ static inline void compute_hflags(CPUMIPSState *env)
>              env->hflags |= MIPS_HFLAG_COP1X;
>          }
>      } else if (env->insn_flags & ISA_MIPS4) {
> -        /* All supported MIPS IV CPUs use the XX (CU3) to enable
> -           and disable the MIPS IV extensions to the MIPS III ISA.
> -           Some other MIPS IV CPUs ignore the bit, so the check here
> -           would be too restrictive for them.  */
> +        /*
> +         * All supported MIPS IV CPUs use the XX (CU3) to enable
> +         * and disable the MIPS IV extensions to the MIPS III ISA.
> +         * Some other MIPS IV CPUs ignore the bit, so the check here
> +         * would be too restrictive for them.
> +         */
>          if (env->CP0_Status & (1U << CP0St_CU3)) {
>              env->hflags |= MIPS_HFLAG_COP1X;
>          }
>