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[Qemu-devel] [PATCH v2 23/32] target/arm: Update arm_mmu_idx for VHE
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 23/32] target/arm: Update arm_mmu_idx for VHE |
Date: |
Wed, 31 Jul 2019 13:38:04 -0700 |
This covers initial generation in arm_mmu_idx, and reconstruction
in core_to_arm_mmu_idx. As a conseqeuence, we also need a bit in
TBFLAGS in order to make the latter reliable.
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/cpu.h | 2 ++
target/arm/helper.c | 42 +++++++++++++++++++++++++++++++-----------
2 files changed, 33 insertions(+), 11 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index b5300f9014..64cda8dbea 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3153,6 +3153,8 @@ FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1)
/* Target EL if we take a floating-point-disabled exception */
FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2)
FIELD(TBFLAG_ANY, BE_DATA, 23, 1)
+/* For A profile only, if EL2 is AA64 and HCR_EL2.E2H is set. */
+FIELD(TBFLAG_ANY, E2H, 22, 1)
/* Bit usage when in AArch32 state: */
FIELD(TBFLAG_A32, THUMB, 0, 1)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 5472424179..578dcfefbf 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11257,21 +11257,29 @@ int fp_exception_el(CPUARMState *env, int cur_el)
ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx)
{
+ bool e2h;
+
if (arm_feature(env, ARM_FEATURE_M)) {
return mmu_idx | ARM_MMU_IDX_M;
}
mmu_idx |= ARM_MMU_IDX_A;
+ if (mmu_idx & ARM_MMU_IDX_S) {
+ return mmu_idx;
+ }
+
+ e2h = (env->cp15.hcr_el2 & HCR_E2H) != 0;
+ if (!arm_el_is_aa64(env, 2)) {
+ e2h = false;
+ }
+
switch (mmu_idx) {
case 0 | ARM_MMU_IDX_A:
- return ARMMMUIdx_EL10_0;
+ return e2h ? ARMMMUIdx_EL20_0 : ARMMMUIdx_EL10_0;
case 1 | ARM_MMU_IDX_A:
return ARMMMUIdx_EL10_1;
case ARMMMUIdx_E2:
- case ARMMMUIdx_SE0:
- case ARMMMUIdx_SE1:
- case ARMMMUIdx_SE3:
- return mmu_idx;
+ return e2h ? ARMMMUIdx_EL20_2 : ARMMMUIdx_E2;
default:
g_assert_not_reached();
}
@@ -11299,24 +11307,28 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState
*env, bool secstate)
ARMMMUIdx arm_mmu_idx(CPUARMState *env)
{
+ bool e2h, sec;
int el;
if (arm_feature(env, ARM_FEATURE_M)) {
return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
}
+ sec = arm_is_secure_below_el3(env);
+ e2h = (env->cp15.hcr_el2 & HCR_E2H) != 0;
+ if (!arm_el_is_aa64(env, 2)) {
+ e2h = false;
+ }
+
el = arm_current_el(env);
switch (el) {
case 0:
- /* TODO: ARMv8.1-VHE */
+ return sec ? ARMMMUIdx_SE0 : e2h ? ARMMMUIdx_EL20_0 : ARMMMUIdx_EL10_0;
case 1:
- return (arm_is_secure_below_el3(env)
- ? ARMMMUIdx_SE0 + el
- : ARMMMUIdx_EL10_0 + el);
+ return sec ? ARMMMUIdx_SE1 : ARMMMUIdx_EL10_1;
case 2:
- /* TODO: ARMv8.1-VHE */
/* TODO: ARMv8.4-SecEL2 */
- return ARMMMUIdx_E2;
+ return e2h ? ARMMMUIdx_EL20_2 : ARMMMUIdx_E2;
case 3:
return ARMMMUIdx_SE3;
default:
@@ -11428,6 +11440,14 @@ void cpu_get_tb_cpu_state(CPUARMState *env,
target_ulong *pc,
flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX,
arm_to_core_mmu_idx(mmu_idx));
+ /*
+ * Include E2H in TBFLAGS so that core_to_arm_mmu_idx can
+ * reliably determine E1&0 vs E2&0 regimes.
+ */
+ if (arm_el_is_aa64(env, 2) && (env->cp15.hcr_el2 & HCR_E2H)) {
+ flags = FIELD_DP32(flags, TBFLAG_ANY, E2H, 1);
+ }
+
/* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
* states defined in the ARM ARM for software singlestep:
* SS_ACTIVE PSTATE.SS State
--
2.17.1
- [Qemu-devel] [PATCH v2 12/32] target/arm: Add VHE system register redirection and aliasing, (continued)
- [Qemu-devel] [PATCH v2 12/32] target/arm: Add VHE system register redirection and aliasing, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 13/32] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 14/32] target/arm: Simplify tlb_force_broadcast alternatives, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 15/32] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_*, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 16/32] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 17/32] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E*, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 18/32] target/arm: Rename ARMMMUIdx_S1SE* to ARMMMUIdx_SE*, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 19/32] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 20/32] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 22/32] target/arm: Add regime_has_2_ranges, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 23/32] target/arm: Update arm_mmu_idx for VHE,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 21/32] target/arm: Reorganize ARMMMUIdx, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 25/32] target/arm: Install asids for E2&0 translation regime, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 24/32] target/arm: Update arm_sctlr for VHE, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 27/32] target/arm: Update arm_phys_excp_target_el for TGE, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 30/32] target/arm: Enable ARMv8.1-VHE in -cpu max, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 28/32] target/arm: Update regime_is_user for EL2&0, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 26/32] target/arm: Flush tlbs for E2&0 translation regime, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 29/32] target/arm: Update {fp, sve}_exception_el for VHE, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 31/32] target/arm: check TGE and E2H flags for EL0 pauth traps, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 32/32] target/arm: generate a custom MIDR for -cpu max, Richard Henderson, 2019/07/31