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[Qemu-devel] [PATCH v2 05/32] target/arm: Install ASIDs for EL2
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 05/32] target/arm: Install ASIDs for EL2 |
Date: |
Wed, 31 Jul 2019 13:37:46 -0700 |
The VMID is the ASID for the 2nd stage page lookup.
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/helper.c | 26 ++++++++++++++++----------
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c0dc76ed41..65e3ffbb43 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3452,17 +3452,23 @@ static void vmsa_ttbr_el1_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = env_archcpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
+ int vmid;
- /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
- if (raw_read(env, ri) != value) {
- tlb_flush_by_mmuidx(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0 |
- ARMMMUIdxBit_S2NS);
- raw_write(env, ri, value);
- }
+ raw_write(env, ri, value);
+
+ /*
+ * TODO: with ARMv8.1-VMID16, aarch64 must examine VTCR.VS
+ * (re-evaluating with changes to VTCR) then use bits [63:48].
+ */
+ vmid = extract64(value, 48, 8);
+
+ /*
+ * A change in VMID to the stage2 page table (S2NS) invalidates
+ * the combined stage 1&2 tlbs (S12NSE1 and S12NSE0).
+ */
+ tlb_set_asid_for_mmuidx(cs, vmid, ARMMMUIdxBit_S2NS,
+ ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0);
}
static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
--
2.17.1
- [Qemu-devel] [PATCH v2 00/32] target/arm: Implement ARMv8.1-VHE, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 01/32] cputlb: Add tlb_set_asid_for_mmuidx, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 02/32] cputlb: Add tlb_flush_asid_by_mmuidx and friends, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 04/32] target/arm: Install ASIDs for short-form from EL1, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 03/32] target/arm: Install ASIDs for long-form from EL1, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 07/32] target/arm: Enable HCR_E2H for VHE, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 06/32] target/arm: Define isar_feature_aa64_vh, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 05/32] target/arm: Install ASIDs for EL2,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 08/32] target/arm: Add CONTEXTIDR_EL2, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 09/32] target/arm: Add TTBR1_EL2, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 10/32] target/arm: Update CNTVCT_EL0 for VHE, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 11/32] target/arm: Add the hypervisor virtual counter, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 12/32] target/arm: Add VHE system register redirection and aliasing, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 13/32] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 14/32] target/arm: Simplify tlb_force_broadcast alternatives, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 15/32] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_*, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 16/32] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2, Richard Henderson, 2019/07/31
- [Qemu-devel] [PATCH v2 17/32] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E*, Richard Henderson, 2019/07/31