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[Qemu-devel] [PATCH-4.2 v2 0/5] RISC-V: Hypervisor prep work part 2
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH-4.2 v2 0/5] RISC-V: Hypervisor prep work part 2 |
Date: |
Tue, 30 Jul 2019 16:35:16 -0700 |
The first three patches are ones that I have pulled out of my original
Hypervisor series at an attempt to reduce the number of patches in the
series.
These three patches all make sense without the Hypervisor series so can
be merged seperatley and will reduce the review burden of the next
version of the patches.
The fource patch is a prep patch for the new v0.4 Hypervisor spec.
The final patch is unreleated to Hypervisor that I'm just slipping in
here because it seems easier then sending it by itself.
v2:
- Small corrections based on feedback
- Remove the CSR permission check patch
Alistair Francis (4):
target/riscv: Don't set write permissions on dirty PTEs
riscv: plic: Remove unused interrupt functions
target/riscv: Create function to test if FP is enabled
target/riscv: Update the Hypervisor CSRs to v0.4
Atish Patra (1):
target/riscv: Fix Floating Point register names
hw/riscv/sifive_plic.c | 12 ------------
include/hw/riscv/sifive_plic.h | 3 ---
target/riscv/cpu.c | 8 ++++----
target/riscv/cpu.h | 6 +++++-
target/riscv/cpu_bits.h | 35 +++++++++++++++++-----------------
target/riscv/cpu_helper.c | 16 ++++++++++++----
target/riscv/csr.c | 20 ++++++++++---------
7 files changed, 50 insertions(+), 50 deletions(-)
--
2.22.0
- [Qemu-devel] [PATCH-4.2 v2 0/5] RISC-V: Hypervisor prep work part 2,
Alistair Francis <=
- [Qemu-devel] [PATCH-4.2 v2 1/5] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/07/30
- [Qemu-devel] [PATCH-4.2 v2 2/5] riscv: plic: Remove unused interrupt functions, Alistair Francis, 2019/07/30
- [Qemu-devel] [PATCH-4.2 v2 3/5] target/riscv: Create function to test if FP is enabled, Alistair Francis, 2019/07/30
- [Qemu-devel] [PATCH-4.2 v2 4/5] target/riscv: Update the Hypervisor CSRs to v0.4, Alistair Francis, 2019/07/30
- [Qemu-devel] [PATCH-4.2 v2 5/5] target/riscv: Fix Floating Point register names, Alistair Francis, 2019/07/30