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Re: [Qemu-devel] [PATCH 04/67] target/arm: Remove offset argument to gen
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 04/67] target/arm: Remove offset argument to gen_exception_internal_insn |
Date: |
Mon, 29 Jul 2019 14:52:42 +0100 |
On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<address@hidden> wrote:
>
> The actual argument is 0 for all callers.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> target/arm/translate.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 19b126d4f3..0848fb933a 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -1239,10 +1239,10 @@ static inline void gen_smc(DisasContext *s)
> s->base.is_jmp = DISAS_SMC;
> }
>
> -static void gen_exception_internal_insn(DisasContext *s, int offset, int
> excp)
> +static void gen_exception_internal_insn(DisasContext *s, int excp)
> {
> gen_set_condexec(s);
> - gen_set_pc_im(s, s->pc - offset);
> + gen_set_pc_im(s, s->pc);
> gen_exception_internal(excp);
> s->base.is_jmp = DISAS_NORETURN;
> }
> @@ -1294,7 +1294,7 @@ static inline void gen_hlt(DisasContext *s, int imm)
> s->current_el != 0 &&
> #endif
> (imm == (s->thumb ? 0x3c : 0xf000))) {
> - gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
> + gen_exception_internal_insn(s, EXCP_SEMIHOST);
> return;
> }
>
> @@ -11984,7 +11984,7 @@ static bool arm_tr_breakpoint_check(DisasContextBase
> *dcbase, CPUState *cpu,
> /* End the TB early; it's likely not going to be executed */
> dc->base.is_jmp = DISAS_TOO_MANY;
> } else {
> - gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
> + gen_exception_internal_insn(dc, EXCP_DEBUG);
> /* The address covered by the breakpoint must be
> included in [tb->pc, tb->pc + tb->size) in order
> to for it to be properly cleared -- thus we
> --
> 2.17.1
I'm not so convinced about this one -- gen_exception_insn()
and gen_exception_internal_insn() shouldn't have the
same pattern of function prototype but different semantics
like this, it's confusing. It happens that both the cases
of wanting to generate an "internal" exception happen to want
it to be taken with the PC being for the following insn,
not the current one, but that seems more coincidence to
me than anything else.
thanks
-- PMM
- [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 01/67] decodetree: Allow !function with no input bits, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 03/67] target/arm: Remove offset argument to gen_exception_bkpt_insn, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 05/67] target/arm: Use the saved value of the insn address, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 04/67] target/arm: Remove offset argument to gen_exception_internal_insn, Richard Henderson, 2019/07/26
- Re: [Qemu-devel] [PATCH 04/67] target/arm: Remove offset argument to gen_exception_internal_insn,
Peter Maydell <=
- [Qemu-devel] [PATCH 06/67] target/arm: Introduce pc_read, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 02/67] target/arm: Remove offset argument to gen_exception_insn, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 07/67] target/arm: Introduce add_reg_for_lit, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 10/67] target/arm: Move test for AL into arm_skip_unless, Richard Henderson, 2019/07/26