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[Qemu-devel] [PATCH 12/67] target/arm: Introduce gen_illegal_op
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 12/67] target/arm: Introduce gen_illegal_op |
Date: |
Fri, 26 Jul 2019 10:49:37 -0700 |
Unify the code sequence for generating an illegal opcode exception.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-vfp.inc.c | 3 +--
target/arm/translate.c | 21 +++++++++++----------
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 4066b2febf..1b08930649 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -108,8 +108,7 @@ static bool full_vfp_access_check(DisasContext *s, bool
ignore_vfp_enabled)
if (!s->vfp_enabled && !ignore_vfp_enabled) {
assert(!arm_dc_feature(s, ARM_FEATURE_M));
- gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
- default_exception_el(s));
+ gen_illegal_op(s);
return false;
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 4738b91957..0f21ee9ce7 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1279,6 +1279,12 @@ static void gen_exception_bkpt_insn(DisasContext *s,
uint32_t syn)
s->base.is_jmp = DISAS_NORETURN;
}
+static void gen_illegal_op(DisasContext *s)
+{
+ gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
+ default_exception_el(s));
+}
+
/* Force a TB lookup after an instruction that changes the CPU state. */
static inline void gen_lookup_tb(DisasContext *s)
{
@@ -1309,8 +1315,7 @@ static inline void gen_hlt(DisasContext *s, int imm)
return;
}
- gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
- default_exception_el(s));
+ gen_illegal_op(s);
}
static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
@@ -7631,8 +7636,7 @@ static void gen_srs(DisasContext *s,
}
if (undef) {
- gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
- default_exception_el(s));
+ gen_illegal_op(s);
return;
}
@@ -9299,8 +9303,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int
insn)
break;
default:
illegal_op:
- gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
- default_exception_el(s));
+ gen_illegal_op(s);
break;
}
}
@@ -10990,8 +10993,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t
insn)
}
return;
illegal_op:
- gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
- default_exception_el(s));
+ gen_illegal_op(s);
}
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
@@ -11816,8 +11818,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
return;
illegal_op:
undef:
- gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(),
- default_exception_el(s));
+ gen_illegal_op(s);
}
static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
--
2.17.1
- [Qemu-devel] [PATCH 06/67] target/arm: Introduce pc_read, (continued)
- [Qemu-devel] [PATCH 06/67] target/arm: Introduce pc_read, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 02/67] target/arm: Remove offset argument to gen_exception_insn, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 07/67] target/arm: Introduce add_reg_for_lit, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 10/67] target/arm: Move test for AL into arm_skip_unless, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 08/67] target/arm: Use store_reg_from_load in thumb2 code, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 12/67] target/arm: Introduce gen_illegal_op,
Richard Henderson <=
- [Qemu-devel] [PATCH 09/67] target/arm: Fold a pc load into load_reg, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 15/67] target/arm: Convert Saturating addition and subtraction, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 16/67] target/arm: Convert Halfword multiply and multiply accumulate, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 14/67] target/arm: Convert multiply and multiply accumulate, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 20/67] target/arm: Convert the rest of A32 Miscelaneous instructions, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 18/67] target/arm: Convert MRS/MSR (banked, register), Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 17/67] target/arm: Convert MSR (immediate) and hints, Richard Henderson, 2019/07/26
- [Qemu-devel] [PATCH 21/67] target/arm: Convert T32 ADDW/SUBW, Richard Henderson, 2019/07/26