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Re: [Qemu-devel] [PATCH v4 20/22] target/arm: Create a TLB entry for tag
Re: [Qemu-devel] [PATCH v4 20/22] target/arm: Create a TLB entry for tag physical address space
Fri, 19 Jul 2019 14:31:48 -0700
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.2
On 7/19/19 8:48 AM, Peter Maydell wrote:
> Playing around with this series, I have discovered that if
> the board model doesn't create the tag-memory then target/arm/cpu.c
> will not create the 'cpu-tag-memory' AddressSpace. But nothing
> disables the usage of the target_tlb_bit2, and then when
> arm_cpu_tlb_fill() does a tlb_set_page_with_attrs() using
> an attrs with target_tlb_bit2 set then we assert in
> cpu_asidx_from_attrs() because cpu->num_ases is 2 and
> cc->asidx_from_attrs() returned an out of range number (ie 2).
> Is the tag-memory mandatory for MTE? If so we should either
> disable MTE if no tag-memory is provided, or else fail
> realize of the CPU; not sure which. If it's not mandatory
> then we need to avoid asserting :-)
I'm not sure. I'll need to study the docs again.
There is an MTE support level at which some of the EL0 bits are recognized but
no tags are supported: ID_AA64PFR0_EL1.MTE == 1. But that's not quite the same
as what you're asking.