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Re: [Qemu-devel] [PATCH for-4.1] target/arm: Set VFP-related MVFR0 field
Re: [Qemu-devel] [PATCH for-4.1] target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026
Thu, 11 Jul 2019 14:43:18 +0200
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On 7/11/19 2:12 PM, Peter Maydell wrote:
> The ARMv5 architecture didn't specify detailed per-feature ID
> registers. Now that we're using the MVFR0 register fields to
> gate the existence of VFP instructions, we need to set up
> the correct values in the cpu->isar structure so that we still
> provide an FPU to the guest.
> This fixes a regression in the arm926 and arm1026 CPUs, which
> are the only ones that both have VFP and are ARMv5 or earlier.
> This regression was introduced by the VFP refactoring, and more
> specifically by commits 1120827fa182f0e76 and 266bd25c485597c,
> which accidentally disabled VFP short-vector support and
> double-precision support on these CPUs.
> Reported-by: Christophe Lyon <address@hidden>
> Signed-off-by: Peter Maydell <address@hidden>
> Fixes: 1120827fa182f0e
> Fixes: 266bd25c485597c
> Fixes: https://bugs.launchpad.net/qemu/+bug/1836192
> I've followed the existing approach we used for ISAR1 here
> of just filling in the fields we care about, rather than trying
> to set the entire register value.
Reviewed-by: Richard Henderson <address@hidden>
> @@ -1713,6 +1719,12 @@ static void arm1026_initfn(Object *obj)
> define_one_arm_cp_reg(cpu, &ifar);
> + /*
> + * Similarly, we need to set MVFR0 fields to enable double precision
> + * and short vector support even though ARMv5 doesn't have this register.
> + */
> + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
> + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
I would have placed this immediately after the Jazelle isar setup, so that the
"Similarly" comment had the proper referent. But, no biggie.