---
Changes in v6:
- Add descriptions from ACPI 6.3 spec
---
hw/acpi/hmat.c | 64 ++++++++++++++++++++++++++++++++++++++++-
hw/acpi/hmat.h | 20 +++++++++++++
include/qemu/typedefs.h | 1 +
include/sysemu/numa.h | 3 ++
include/sysemu/sysemu.h | 2 ++
5 files changed, 89 insertions(+), 1 deletion(-)
diff --git a/hw/acpi/hmat.c b/hw/acpi/hmat.c
index 6dd39b0c85..a207581f11 100644
--- a/hw/acpi/hmat.c
+++ b/hw/acpi/hmat.c
@@ -133,14 +133,63 @@ static void build_hmat_lb(GArray *table_data,
HMAT_LB_Info *numa_hmat_lb,
}
}
+/* ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure: Table 5-143 */
+static void build_hmat_cache(GArray *table_data, HMAT_Cache_Info *hmat_cache)
+{
+ /*
+ * Cache Attributes: Bits [3:0] ?C Total Cache Levels
+ * for this Memory Proximity Domain
+ */
+ uint32_t cache_attr = hmat_cache->total_levels & 0xF;
+
+ /* Bits [7:4] : Cache Level described in this structure */
+ cache_attr |= (hmat_cache->level & 0xF) << 4;
+
+ /* Bits [11:8] - Cache Associativity */
+ cache_attr |= (hmat_cache->associativity & 0xF) << 8;
+
+ /* Bits [15:12] - Write Policy */
+ cache_attr |= (hmat_cache->write_policy & 0xF) << 12;
+
+ /* Bits [31:16] - Cache Line size in bytes */
+ cache_attr |= (hmat_cache->line_size & 0xFFFF) << 16;
+
+ cache_attr = cpu_to_le32(cache_attr);
+
+ /* Type */
+ build_append_int_noprefix(table_data, 2, 2);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 2);
+ /* Length */
+ build_append_int_noprefix(table_data, 32, 4);
+ /* Proximity Domain for the Memory */
+ build_append_int_noprefix(table_data, hmat_cache->mem_proximity, 4);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 4);
+ /* Memory Side Cache Size */
+ build_append_int_noprefix(table_data, hmat_cache->size, 8);
+ /* Cache Attributes */
+ build_append_int_noprefix(table_data, cache_attr, 4);
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 2);
+ /*
+ * Number of SMBIOS handles (n)
+ * Linux kernel uses Memory Side Cache Information Structure
+ * without SMBIOS entries for now, so set Number of SMBIOS handles
+ * as 0.
+ */
+ build_append_int_noprefix(table_data, 0, 2);
+}
+
/* Build HMAT sub table structures */
static void hmat_build_table_structs(GArray *table_data, NumaState *nstat)
{
uint16_t flags;
uint32_t num_initiator = 0;
uint32_t initiator_pxm[MAX_NODES];
- int i, hrchy, type;
+ int i, hrchy, type, level;
HMAT_LB_Info *numa_hmat_lb;
+ HMAT_Cache_Info *numa_hmat_cache;
for (i = 0; i < nstat->num_nodes; i++) {
flags = 0;
@@ -174,6 +223,19 @@ static void hmat_build_table_structs(GArray *table_data,
NumaState *nstat)
}
}
}
+
+ /*
+ * ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure:
+ * Table 5-143
+ */
+ for (i = 0; i < nstat->num_nodes; i++) {
+ for (level = 0; level <= MAX_HMAT_CACHE_LEVEL; level++) {
+ numa_hmat_cache = nstat->hmat_cache[i][level];
+ if (numa_hmat_cache) {
+ build_hmat_cache(table_data, numa_hmat_cache);
+ }
+ }
+ }
}
void build_hmat(GArray *table_data, BIOSLinker *linker, NumaState *nstat)
diff --git a/hw/acpi/hmat.h b/hw/acpi/hmat.h
index 9d5f407b8a..ba655281cc 100644
--- a/hw/acpi/hmat.h
+++ b/hw/acpi/hmat.h
@@ -79,6 +79,26 @@ struct HMAT_LB_Info {
uint16_t bandwidth[MAX_NODES][MAX_NODES];
};
+struct HMAT_Cache_Info {
+ /* The memory proximity domain to which the memory belongs. */
+ uint32_t mem_proximity;
+ /* Size of memory side cache in bytes. */
+ uint64_t size;
+ /*
+ * Total cache levels for this memory
+ * pr#include "hw/acpi/aml-build.h"oximity domain.