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[Qemu-devel] [PULL v6 05/42] hw/riscv: Replace global smp variables with
From: |
Eduardo Habkost |
Subject: |
[Qemu-devel] [PULL v6 05/42] hw/riscv: Replace global smp variables with machine smp properties |
Date: |
Fri, 5 Jul 2019 19:14:27 -0300 |
From: Like Xu <address@hidden>
The global smp variables in riscv are replaced with smp machine properties.
A local variable of the same name would be introduced in the declaration
phase if it's used widely in the context OR replace it on the spot if it's
only used once. No semantic changes.
Signed-off-by: Like Xu <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
[ehabkost: fix spike_board_init()]
[ehabkost: fix riscv_sifive_e_soc_init()]
Signed-off-by: Eduardo Habkost <address@hidden>
---
hw/riscv/sifive_e.c | 6 ++++--
hw/riscv/sifive_plic.c | 3 +++
hw/riscv/sifive_u.c | 11 +++++++----
hw/riscv/spike.c | 3 +++
hw/riscv/virt.c | 1 +
5 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index d27f626529..2a499d8ed2 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -124,6 +124,7 @@ static void riscv_sifive_e_init(MachineState *machine)
static void riscv_sifive_e_soc_init(Object *obj)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
SiFiveESoCState *s = RISCV_E_SOC(obj);
object_initialize_child(obj, "cpus", &s->cpus,
@@ -131,7 +132,7 @@ static void riscv_sifive_e_soc_init(Object *obj)
&error_abort, NULL);
object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type",
&error_abort);
- object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
+ object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
&error_abort);
sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0",
&s->gpio, sizeof(s->gpio),
@@ -140,6 +141,7 @@ static void riscv_sifive_e_soc_init(Object *obj)
static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
const struct MemmapEntry *memmap = sifive_e_memmap;
Error *err = NULL;
@@ -168,7 +170,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev,
Error **errp)
SIFIVE_E_PLIC_CONTEXT_STRIDE,
memmap[SIFIVE_E_PLIC].size);
sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
- memmap[SIFIVE_E_CLINT].size, smp_cpus,
+ memmap[SIFIVE_E_CLINT].size, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index 70a4413599..0950e89e15 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -24,6 +24,7 @@
#include "qemu/error-report.h"
#include "hw/sysbus.h"
#include "hw/pci/msi.h"
+#include "hw/boards.h"
#include "target/riscv/cpu.h"
#include "sysemu/sysemu.h"
#include "hw/riscv/sifive_plic.h"
@@ -439,6 +440,8 @@ static void sifive_plic_irq_request(void *opaque, int irq,
int level)
static void sifive_plic_realize(DeviceState *dev, Error **errp)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
+ unsigned int smp_cpus = ms->smp.cpus;
SiFivePLICState *plic = SIFIVE_PLIC(dev);
int i;
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 4208671552..ca53a9290d 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -315,13 +315,14 @@ static void riscv_sifive_u_init(MachineState *machine)
static void riscv_sifive_u_soc_init(Object *obj)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
SiFiveUSoCState *s = RISCV_U_SOC(obj);
object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus),
TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type",
&error_abort);
- object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
+ object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
&error_abort);
sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
@@ -330,6 +331,7 @@ static void riscv_sifive_u_soc_init(Object *obj)
static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
SiFiveUSoCState *s = RISCV_U_SOC(dev);
const struct MemmapEntry *memmap = sifive_u_memmap;
MemoryRegion *system_memory = get_system_memory();
@@ -351,9 +353,10 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev,
Error **errp)
mask_rom);
/* create PLIC hart topology configuration string */
- plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * smp_cpus;
+ plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
+ ms->smp.cpus;
plic_hart_config = g_malloc0(plic_hart_config_len);
- for (i = 0; i < smp_cpus; i++) {
+ for (i = 0; i < ms->smp.cpus; i++) {
if (i != 0) {
strncat(plic_hart_config, ",", plic_hart_config_len);
}
@@ -379,7 +382,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev,
Error **errp)
sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
- memmap[SIFIVE_U_CLINT].size, smp_cpus,
+ memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index e68be00a5f..2991b341a2 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -159,6 +159,7 @@ static void spike_board_init(MachineState *machine)
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
int i;
+ unsigned int smp_cpus = machine->smp.cpus;
/* Initialize SOC */
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
@@ -241,6 +242,7 @@ static void spike_v1_10_0_board_init(MachineState *machine)
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
int i;
+ unsigned int smp_cpus = machine->smp.cpus;
if (!qtest_enabled()) {
info_report("The Spike v1.10.0 machine has been deprecated. "
@@ -329,6 +331,7 @@ static void spike_v1_09_1_board_init(MachineState *machine)
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
int i;
+ unsigned int smp_cpus = machine->smp.cpus;
if (!qtest_enabled()) {
info_report("The Spike v1.09.1 machine has been deprecated. "
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index d8181a4ff1..ecdc77d728 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -371,6 +371,7 @@ static void riscv_virt_board_init(MachineState *machine)
char *plic_hart_config;
size_t plic_hart_config_len;
int i;
+ unsigned int smp_cpus = machine->smp.cpus;
void *fdt;
/* Initialize SOC */
--
2.18.0.rc1.1.g3f1ff2140
- [Qemu-devel] [PULL v6 00/42] Machine and x86 queue, 2019-07-05, Eduardo Habkost, 2019/07/05
- [Qemu-devel] [PULL v6 04/42] hw/ppc: Replace global smp variables with machine smp properties, Eduardo Habkost, 2019/07/05
- [Qemu-devel] [PULL v6 01/42] hw/boards: Add struct CpuTopology to MachineState, Eduardo Habkost, 2019/07/05
- [Qemu-devel] [PULL v6 02/42] machine: Refactor smp-related call chains to pass MachineState, Eduardo Habkost, 2019/07/05
- [Qemu-devel] [PULL v6 05/42] hw/riscv: Replace global smp variables with machine smp properties,
Eduardo Habkost <=
- [Qemu-devel] [PULL v6 06/42] hw/s390x: Replace global smp variables with machine smp properties, Eduardo Habkost, 2019/07/05
- [Qemu-devel] [PULL v6 03/42] general: Replace global smp variables with smp machine properties, Eduardo Habkost, 2019/07/05
- [Qemu-devel] [PULL v6 07/42] hw/i386: Replace global smp variables with machine smp properties, Eduardo Habkost, 2019/07/05
- [Qemu-devel] [PULL v6 09/42] hw: Replace global smp variables with MachineState for all remaining archs, Eduardo Habkost, 2019/07/05
- [Qemu-devel] [PULL v6 12/42] hw/i386: Adjust nr_dies with configured smp_dies for PCMachine, Eduardo Habkost, 2019/07/05
- [Qemu-devel] [PULL v6 10/42] vl.c: Replace smp global variables with smp machine properties, Eduardo Habkost, 2019/07/05
- [Qemu-devel] [PULL v6 13/42] i386/cpu: Consolidate die-id validity in smp context, Eduardo Habkost, 2019/07/05
- [Qemu-devel] [PULL v6 08/42] hw/arm: Replace global smp variables with machine smp properties, Eduardo Habkost, 2019/07/05