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[Qemu-devel] [PULL 2/9] target/arm: Restrict semi-hosting to TCG
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 2/9] target/arm: Restrict semi-hosting to TCG |
Date: |
Thu, 4 Jul 2019 17:07:55 +0100 |
From: Philippe Mathieu-Daudé <address@hidden>
Per Peter Maydell:
Semihosting hooks either SVC or HLT instructions, and inside KVM
both of those go to EL1, ie to the guest, and can't be trapped to
KVM.
Let check_for_semihosting() return False when not running on TCG.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/Makefile.objs | 2 +-
target/arm/cpu.h | 7 +++++++
target/arm/helper.c | 8 +++++++-
3 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index 294433da880..82bedefc3d0 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -1,4 +1,4 @@
-obj-y += arm-semi.o
+obj-$(CONFIG_TCG) += arm-semi.o
obj-y += helper.o vfp_helper.o
obj-y += cpu.o gdbstub.o
obj-$(TARGET_AARCH64) += cpu64.o gdbstub64.o
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a9be18660fd..94c990cddbd 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -964,7 +964,14 @@ static inline void aarch64_sve_change_el(CPUARMState *env,
int o,
{ }
#endif
+#if !defined(CONFIG_TCG)
+static inline target_ulong do_arm_semihosting(CPUARMState *env)
+{
+ g_assert_not_reached();
+}
+#else
target_ulong do_arm_semihosting(CPUARMState *env);
+#endif
void aarch64_sync_32_to_64(CPUARMState *env);
void aarch64_sync_64_to_32(CPUARMState *env);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9a1fe3b72ed..055bf831a61 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -20,7 +20,6 @@
#include "qemu/qemu-print.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
-#include "arm_ldst.h"
#include <zlib.h> /* For crc32 */
#include "hw/semihosting/semihost.h"
#include "sysemu/cpus.h"
@@ -29,6 +28,9 @@
#include "qapi/qapi-commands-machine-target.h"
#include "qapi/error.h"
#include "qemu/guest-random.h"
+#ifdef CONFIG_TCG
+#include "arm_ldst.h"
+#endif
#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
@@ -10399,6 +10401,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
static inline bool check_for_semihosting(CPUState *cs)
{
+#ifdef CONFIG_TCG
/* Check whether this exception is a semihosting call; if so
* then handle it and return true; otherwise return false.
*/
@@ -10474,6 +10477,9 @@ static inline bool check_for_semihosting(CPUState *cs)
env->regs[0] = do_arm_semihosting(env);
return true;
}
+#else
+ return false;
+#endif
}
/* Handle a CPU exception for A and R profile CPUs.
--
2.20.1
- [Qemu-devel] [PULL 0/9] target-arm queue, Peter Maydell, 2019/07/04
- [Qemu-devel] [PULL 2/9] target/arm: Restrict semi-hosting to TCG,
Peter Maydell <=
- [Qemu-devel] [PULL 1/9] target/arm: Move debug routines to debug_helper.c, Peter Maydell, 2019/07/04
- [Qemu-devel] [PULL 6/9] target/arm: Use _ra versions of cpu_stl_data() in v7M helpers, Peter Maydell, 2019/07/04
- [Qemu-devel] [PULL 5/9] target/arm: v8M: Check state of exception being returned from, Peter Maydell, 2019/07/04
- [Qemu-devel] [PULL 7/9] hw/timer/armv7m_systick: Forbid non-privileged accesses, Peter Maydell, 2019/07/04
- [Qemu-devel] [PULL 8/9] target/arm: Execute Thumb instructions when their condbits are 0xf, Peter Maydell, 2019/07/04
- [Qemu-devel] [PULL 9/9] target/arm: Correct VMOV_imm_dp handling of short vectors, Peter Maydell, 2019/07/04
- [Qemu-devel] [PULL 4/9] arm v8M: Forcibly clear negative-priority exceptions on deactivate, Peter Maydell, 2019/07/04
- [Qemu-devel] [PULL 3/9] target/arm/helper: Move M profile routines to m_helper.c, Peter Maydell, 2019/07/04
- Re: [Qemu-devel] [PULL 0/9] target-arm queue, Peter Maydell, 2019/07/04
- Re: [Qemu-devel] [PULL 0/9] target-arm queue, no-reply, 2019/07/05