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[Qemu-devel] [PULL 25/46] aspeed: Link SCU to the watchdog
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 25/46] aspeed: Link SCU to the watchdog |
Date: |
Mon, 1 Jul 2019 17:39:22 +0100 |
From: Joel Stanley <address@hidden>
The ast2500 uses the watchdog to reset the SDRAM controller. This
operation is usually performed by u-boot's memory training procedure,
and it is enabled by setting a bit in the SCU and then causing the
watchdog to expire. Therefore, we need the watchdog to be able to
access the SCU's register space.
This causes the watchdog to not perform a system reset when the bit is
set. In the future it could perform a reset of the SDMC model.
Signed-off-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
include/hw/watchdog/wdt_aspeed.h | 1 +
hw/arm/aspeed_soc.c | 2 ++
hw/watchdog/wdt_aspeed.c | 20 ++++++++++++++++++++
3 files changed, 23 insertions(+)
diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
index 88d8be4f78d..daef0c0e230 100644
--- a/include/hw/watchdog/wdt_aspeed.h
+++ b/include/hw/watchdog/wdt_aspeed.h
@@ -27,6 +27,7 @@ typedef struct AspeedWDTState {
MemoryRegion iomem;
uint32_t regs[ASPEED_WDT_REGS_MAX];
+ AspeedSCUState *scu;
uint32_t pclk_freq;
uint32_t silicon_rev;
uint32_t ext_pulse_width_mask;
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 443e4c49f21..c6fb3700f27 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -235,6 +235,8 @@ static void aspeed_soc_init(Object *obj)
sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev",
sc->info->silicon_rev);
+ object_property_add_const_link(OBJECT(&s->wdt[i]), "scu",
+ OBJECT(&s->scu), &error_abort);
}
for (i = 0; i < ASPEED_MACS_NUM; i++) {
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
index 4a8409f0daf..57fe24ae6b1 100644
--- a/hw/watchdog/wdt_aspeed.c
+++ b/hw/watchdog/wdt_aspeed.c
@@ -44,6 +44,9 @@
#define WDT_RESTART_MAGIC 0x4755
+#define SCU_RESET_CONTROL1 (0x04 / 4)
+#define SCU_RESET_SDRAM BIT(0)
+
static bool aspeed_wdt_is_enabled(const AspeedWDTState *s)
{
return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE;
@@ -222,6 +225,13 @@ static void aspeed_wdt_timer_expired(void *dev)
{
AspeedWDTState *s = ASPEED_WDT(dev);
+ /* Do not reset on SDRAM controller reset */
+ if (s->scu->regs[SCU_RESET_CONTROL1] & SCU_RESET_SDRAM) {
+ timer_del(s->timer);
+ s->regs[WDT_CTRL] = 0;
+ return;
+ }
+
qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n");
watchdog_perform_action();
timer_del(s->timer);
@@ -233,6 +243,16 @@ static void aspeed_wdt_realize(DeviceState *dev, Error
**errp)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
AspeedWDTState *s = ASPEED_WDT(dev);
+ Error *err = NULL;
+ Object *obj;
+
+ obj = object_property_get_link(OBJECT(dev), "scu", &err);
+ if (!obj) {
+ error_propagate(errp, err);
+ error_prepend(errp, "required link 'scu' not found: ");
+ return;
+ }
+ s->scu = ASPEED_SCU(obj);
if (!is_supported_silicon_rev(s->silicon_rev)) {
error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
--
2.20.1
- [Qemu-devel] [PULL 36/46] target/arm: Move the DC ZVA helper into op_helper, (continued)
- [Qemu-devel] [PULL 36/46] target/arm: Move the DC ZVA helper into op_helper, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 29/46] target/arm: Makefile cleanup (ARM), Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 05/46] i.mx7d: Add no-op/unimplemented PCIE PHY IP block, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 13/46] aspeed: introduce a configurable number of CPU per machine, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 07/46] pci: designware: Update MSI mapping when MSI address changes, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 42/46] target/arm/vfp_helper: Extract vfp_set_fpscr_from_host(), Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 40/46] target/arm/vfp_helper: Move code around, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 35/46] target/arm: Fix coding style issues, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 23/46] hw/misc/aspeed_xdma: New device, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 10/46] aspeed: add a per SoC mapping for the memory space, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 25/46] aspeed: Link SCU to the watchdog,
Peter Maydell <=
- [Qemu-devel] [PULL 18/46] aspeed/timer: Ensure positive muldiv delta, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 33/46] target/arm/helper: Remove unused include, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 43/46] target/arm/vfp_helper: Restrict the SoftFloat use to TCG, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 41/46] target/arm/vfp_helper: Extract vfp_set_fpscr_to_host(), Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 12/46] hw/arm/aspeed: Add RTC to SoC, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 31/46] target/arm: Makefile cleanup (softmmu), Peter Maydell, 2019/07/01
- Re: [Qemu-devel] [PULL 00/46] target-arm queue, Peter Maydell, 2019/07/02