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[Qemu-devel] [PULL 44/46] target/arm: Restrict PSCI to TCG
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 44/46] target/arm: Restrict PSCI to TCG |
Date: |
Mon, 1 Jul 2019 17:39:41 +0100 |
From: Philippe Mathieu-Daudé <address@hidden>
Under KVM, the kernel gets the HVC call and handle the PSCI requests.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/internals.h | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 46a1313d69d..57e0253ef48 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -529,11 +529,15 @@ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr
addr, int len);
/* Callback function for when a watchpoint or breakpoint triggers. */
void arm_debug_excp_handler(CPUState *cs);
-#ifdef CONFIG_USER_ONLY
+#if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG)
static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
{
return false;
}
+static inline void arm_handle_psci_call(ARMCPU *cpu)
+{
+ g_assert_not_reached();
+}
#else
/* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call.
*/
bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
--
2.20.1
- [Qemu-devel] [PULL 14/46] aspeed: add support for multiple NICs, (continued)
- [Qemu-devel] [PULL 14/46] aspeed: add support for multiple NICs, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 01/46] hw/arm/boot: fix direct kernel boot with initrd, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 34/46] target/arm: Fix multiline comment syntax, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 08/46] i.mx7d: pci: Update PCI IRQ mapping to match HW, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 45/46] target/arm: Declare arm_log_exception() function publicly, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 17/46] aspeed/timer: Fix match calculations, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 22/46] aspeed: Add support for the swift-bmc board, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 28/46] target/arm: Makefile cleanup (Aarch64), Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 09/46] aspeed: add a per SoC mapping for the interrupt space, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 27/46] hw/arm: Add arm SBSA reference machine, devices part, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 44/46] target/arm: Restrict PSCI to TCG,
Peter Maydell <=
- [Qemu-devel] [PULL 32/46] target/arm: Add copyright boilerplate, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 19/46] aspeed: remove the "ram" link, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 20/46] aspeed: add a RAM memory region container, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 46/46] target/arm: Declare some M-profile functions publicly, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 24/46] aspeed: vic: Add support for legacy register interface, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 02/46] hw/arm/msf2-som: Exit when the cpu is not the expected one, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 38/46] target/arm: Declare get_phys_addr() function publicly, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 37/46] target/arm: Move CPU state dumping routines to cpu.c, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 06/46] pci: designware: Update MSI mapping unconditionally, Peter Maydell, 2019/07/01
- [Qemu-devel] [PULL 21/46] aspeed/smc: add a 'sdram_base' property, Peter Maydell, 2019/07/01