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[Qemu-devel] [RISU RFC PATCH v2 11/14] x86.risu: add SSE4.1 and SSE4.2 i
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From: |
Jan Bobek |
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Subject: |
[Qemu-devel] [RISU RFC PATCH v2 11/14] x86.risu: add SSE4.1 and SSE4.2 instructions |
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Date: |
Mon, 1 Jul 2019 00:35:33 -0400 |
Add SSE4.1 and SSE4.2 instructions to the x86 configuration file.
Signed-off-by: Jan Bobek <address@hidden>
---
x86.risu | 69 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/x86.risu b/x86.risu
index 35992d6..a73e209 100644
--- a/x86.risu
+++ b/x86.risu
@@ -124,10 +124,12 @@ ADDSUBPD SSE3 00001111 11010000 !emit {
data16(); modrm(); mem(size =>
PMULLW MMX 00001111 11010101 !emit { modrm(); mem(size => 8); }
PMULLW SSE2 00001111 11010101 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+PMULLD SSE4_1 00001111 00111000 01000000 !emit { data16(); modrm();
mem(size => 16, align => 16); }
PMULHW MMX 00001111 11100101 !emit { modrm(); mem(size => 8); }
PMULHW SSE2 00001111 11100101 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PMULHUW SSE 00001111 11100100 !emit { modrm(); mem(size => 8); }
PMULHUW SSE2 00001111 11100100 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+PMULDQ SSE4_1 00001111 00111000 00101000 !emit { data16(); modrm();
mem(size => 16, align => 16); }
PMULUDQ_64 SSE2 00001111 11110100 !emit { modrm(); mem(size => 8); }
PMULUDQ SSE2 00001111 11110100 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
@@ -162,18 +164,28 @@ RSQRTSS SSE 00001111 01010010 !emit { rep();
modrm(); mem(size => 4)
PMINUB SSE 00001111 11011010 !emit { modrm(); mem(size => 8); }
PMINUB SSE2 00001111 11011010 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+PMINUW SSE4_1 00001111 00111000 00111010 !emit { data16(); modrm();
mem(size => 16, align => 16); }
+PMINUD SSE4_1 00001111 00111000 00111011 !emit { data16(); modrm();
mem(size => 16, align => 16); }
+PMINSB SSE4_1 00001111 00111000 00111000 !emit { data16(); modrm();
mem(size => 16, align => 16); }
PMINSW SSE 00001111 11101010 !emit { modrm(); mem(size => 8); }
PMINSW SSE2 00001111 11101010 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+PMINSD SSE4_1 00001111 00111000 00111001 !emit { data16(); modrm();
mem(size => 16, align => 16); }
MINPS SSE 00001111 01011101 !emit { modrm(); mem(size => 16,
align => 16); }
MINPD SSE2 00001111 01011101 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
MINSS SSE 00001111 01011101 !emit { rep(); modrm(); mem(size =>
4); }
MINSD SSE2 00001111 01011101 !emit { repne(); modrm(); mem(size
=> 8); }
+PHMINPOSUW SSE4_1 00001111 00111000 01000001 !emit { data16(); modrm();
mem(size => 16, align => 16); }
+
PMAXUB SSE 00001111 11011110 !emit { modrm(); mem(size => 8); }
PMAXUB SSE2 00001111 11011110 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+PMAXUW SSE4_1 00001111 00111000 00111110 !emit { data16(); modrm();
mem(size => 16, align => 16); }
+PMAXUD SSE4_1 00001111 00111000 00111111 !emit { data16(); modrm();
mem(size => 16, align => 16); }
+PMAXSB SSE4_1 00001111 00111000 00111100 !emit { data16(); modrm();
mem(size => 16, align => 16); }
PMAXSW SSE 00001111 11101110 !emit { modrm(); mem(size => 8); }
PMAXSW SSE2 00001111 11101110 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+PMAXSD SSE4_1 00001111 00111000 00111101 !emit { data16(); modrm();
mem(size => 16, align => 16); }
MAXPS SSE 00001111 01011111 !emit { modrm(); mem(size => 16,
align => 16); }
MAXPD SSE2 00001111 01011111 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
@@ -187,6 +199,7 @@ PAVGW SSE2 00001111 11100011 !emit { data16();
modrm(); mem(size =>
PSADBW SSE 00001111 11110110 !emit { modrm(); mem(size => 8); }
PSADBW SSE2 00001111 11110110 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+MPSADBW SSE4_1 00001111 00111010 01000010 !emit { data16(); modrm();
mem(size => 16, align => 16); imm(size => 1); }
PABSB_64 SSSE3 00001111 00111000 00011100 !emit { modrm(); mem(size
=> 8); }
PABSB SSSE3 00001111 00111000 00011100 !emit { data16(); modrm();
mem(size => 16, align => 16); }
@@ -202,6 +215,14 @@ PSIGNW SSSE3 00001111 00111000 00001001 !emit {
data16(); modrm(); me
PSIGND_64 SSSE3 00001111 00111000 00001010 !emit { modrm(); mem(size
=> 8); }
PSIGND SSSE3 00001111 00111000 00001010 !emit { data16(); modrm();
mem(size => 16, align => 16); }
+DPPS SSE4_1 00001111 00111010 01000000 !emit { data16(); modrm();
mem(size => 16, align => 16); imm(size => 1); }
+DPPD SSE4_1 00001111 00111010 01000001 !emit { data16(); modrm();
mem(size => 16, align => 16); imm(size => 1); }
+
+ROUNDPS SSE4_1 00001111 00111010 00001000 !emit { data16(); modrm();
mem(size => 16, align => 16); imm(size => 1); }
+ROUNDPD SSE4_1 00001111 00111010 00001001 !emit { data16(); modrm();
mem(size => 16, align => 16); imm(size => 1); }
+ROUNDSS SSE4_1 00001111 00111010 00001010 !emit { data16(); modrm();
mem(size => 4); imm(size => 1); }
+ROUNDSD SSE4_1 00001111 00111010 00001011 !emit { data16(); modrm();
mem(size => 8); imm(size => 1); }
+
# Comparison Instructions
PCMPEQB MMX 00001111 01110100 !emit { modrm(); mem(size => 8); }
PCMPEQB SSE2 00001111 01110100 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
@@ -209,12 +230,21 @@ PCMPEQW MMX 00001111 01110101 !emit {
modrm(); mem(size => 8); }
PCMPEQW SSE2 00001111 01110101 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PCMPEQD MMX 00001111 01110110 !emit { modrm(); mem(size => 8); }
PCMPEQD SSE2 00001111 01110110 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+PCMPEQQ SSE4_1 00001111 00111000 00101001 !emit { data16(); modrm();
mem(size => 16, align => 16); }
PCMPGTB MMX 00001111 01100100 !emit { modrm(); mem(size => 8); }
PCMPGTB SSE2 00001111 01100100 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PCMPGTW MMX 00001111 01100101 !emit { modrm(); mem(size => 8); }
PCMPGTW SSE2 00001111 01100101 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PCMPGTD MMX 00001111 01100110 !emit { modrm(); mem(size => 8); }
PCMPGTD SSE2 00001111 01100110 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+PCMPGTQ SSE4_2 00001111 00111000 00110111 !emit { data16(); modrm();
mem(size => 16, align => 16); }
+
+PCMPESTRM SSE4_2 00001111 00111010 01100000 !emit { data16(); modrm();
mem(size => 16); imm(size => 1); }
+PCMPESTRI SSE4_2 00001111 00111010 01100001 !emit { data16(); modrm();
mem(size => 16); imm(size => 1); }
+PCMPISTRM SSE4_2 00001111 00111010 01100010 !emit { data16(); modrm();
mem(size => 16); imm(size => 1); }
+PCMPISTRI SSE4_2 00001111 00111010 01100011 !emit { data16(); modrm();
mem(size => 16); imm(size => 1); }
+
+PTEST SSE4_1 00001111 00111000 00010111 !emit { data16(); modrm();
mem(size => 16, align => 16); }
CMPPS SSE 00001111 11000010 !emit { modrm(); mem(size => 16,
align => 16); imm(size => 1); }
CMPPD SSE2 00001111 11000010 !emit { data16(); modrm(); mem(size
=> 16, align => 16); imm(size => 1); }
@@ -299,6 +329,7 @@ PACKSSDW MMX 00001111 01101011 !emit { modrm();
mem(size => 8); }
PACKSSDW SSE2 00001111 01101011 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
PACKUSWB MMX 00001111 01100111 !emit { modrm(); mem(size => 8); }
PACKUSWB SSE2 00001111 01100111 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
+PACKUSDW SSE4_1 00001111 00111000 00101011 !emit { data16(); modrm();
mem(size => 16, align => 16); }
PUNPCKHBW MMX 00001111 01101000 !emit { modrm(); mem(size => 8); }
PUNPCKHBW SSE2 00001111 01101000 !emit { data16(); modrm(); mem(size
=> 16, align => 16); }
@@ -331,13 +362,50 @@ PSHUFD SSE2 00001111 01110000 !emit {
data16(); modrm(); mem(size =>
SHUFPS SSE 00001111 11000110 !emit { modrm(); mem(size => 16,
align => 16); imm(size => 1); }
SHUFPD SSE2 00001111 11000110 !emit { data16(); modrm(); mem(size
=> 16, align => 16); imm(size => 1); }
+BLENDPS SSE4_1 00001111 00111010 00001100 !emit { data16(); modrm();
mem(size => 16, align => 16); imm(size => 1); }
+BLENDPD SSE4_1 00001111 00111010 00001101 !emit { data16(); modrm();
mem(size => 16, align => 16); imm(size => 1); }
+BLENDVPS SSE4_1 00001111 00111000 00010100 !emit { data16(); modrm();
mem(size => 16, align => 16); }
+BLENDVPD SSE4_1 00001111 00111000 00010101 !emit { data16(); modrm();
mem(size => 16, align => 16); }
+PBLENDVB SSE4_1 00001111 00111000 00010000 !emit { data16(); modrm();
mem(size => 16, align => 16); }
+PBLENDW SSE4_1 00001111 00111010 00001110 !emit { data16(); modrm();
mem(size => 16, align => 16); imm(size => 1); }
+
+INSERTPS SSE4_1 00001111 00111010 00100001 !emit { data16(); modrm();
mem(size => 4); imm(size => 1); }
+PINSRB SSE4_1 00001111 00111010 00100000 !emit { data16(); modrm();
mem(size => 1); imm(size => 1); }
PINSRW SSE 00001111 11000100 !emit { modrm(); mem(size => 2);
imm(size => 1); }
PINSRW SSE2 00001111 11000100 !emit { data16(); modrm(); mem(size
=> 2); imm(size => 1); }
+PINSRD SSE4_1 00001111 00111010 00100010 !emit { data16(); modrm();
mem(size => 4); imm(size => 1); }
+PINSRQ SSE4_1 00001111 00111010 00100010 !emit { data16(); rex(w =>
1); modrm(); mem(size => 8); imm(size => 1); }
+
+EXTRACTPS SSE4_1 00001111 00111010 00010111 !emit { data16(); modrm(mod
=> MOD_DIRECT, rm => ~REG_ESP); imm(size => 1); }
+EXTRACTPS_mem SSE4_1 00001111 00111010 00010111 !emit { data16(); modrm(mod
=> ~MOD_DIRECT); mem(size => 4); imm(size => 1); }
+
+PEXTRB SSE4_1 00001111 00111010 00010100 !emit { data16(); modrm(mod
=> MOD_DIRECT, rm => ~REG_ESP); imm(size => 1); }
+PEXTRB_mem SSE4_1 00001111 00111010 00010100 !emit { data16(); modrm(mod
=> ~MOD_DIRECT); mem(size => 1); imm(size => 1); }
+PEXTRW SSE4_1 00001111 00111010 00010101 !emit { data16(); modrm(mod
=> MOD_DIRECT, rm => ~REG_ESP); imm(size => 1); }
+PEXTRW_mem SSE4_1 00001111 00111010 00010101 !emit { data16(); modrm(mod
=> ~MOD_DIRECT); mem(size => 2); imm(size => 1); }
+PEXTRD SSE4_1 00001111 00111010 00010110 !emit { data16(); modrm(mod
=> MOD_DIRECT, rm => ~REG_ESP); imm(size => 1); }
+PEXTRD_mem SSE4_1 00001111 00111010 00010110 !emit { data16(); modrm(mod
=> ~MOD_DIRECT); mem(size => 4); imm(size => 1); }
+PEXTRQ SSE4_1 00001111 00111010 00010110 !emit { data16(); rex(w =>
1); modrm(mod => MOD_DIRECT, rm => ~REG_ESP); imm(size => 1); }
+PEXTRQ_mem SSE4_1 00001111 00111010 00010110 !emit { data16(); rex(w =>
1); modrm(mod => ~MOD_DIRECT); mem(size => 8); imm(size => 1); }
PEXTRW_reg SSE 00001111 11000101 !emit { modrm(mod => MOD_DIRECT, reg
=> ~REG_ESP); imm(size => 1); }
PEXTRW_reg SSE2 00001111 11000101 !emit { data16(); modrm(mod =>
MOD_DIRECT, reg => ~REG_ESP); imm(size => 1); }
# Conversion Instructions
+PMOVSXBW SSE4_1 00001111 00111000 00100000 !emit { data16(); modrm();
mem(size => 8); }
+PMOVSXBD SSE4_1 00001111 00111000 00100001 !emit { data16(); modrm();
mem(size => 4); }
+PMOVSXBQ SSE4_1 00001111 00111000 00100010 !emit { data16(); modrm();
mem(size => 2); }
+PMOVSXWD SSE4_1 00001111 00111000 00100011 !emit { data16(); modrm();
mem(size => 8); }
+PMOVSXWQ SSE4_1 00001111 00111000 00100100 !emit { data16(); modrm();
mem(size => 4); }
+PMOVSXDQ SSE4_1 00001111 00111000 00100101 !emit { data16(); modrm();
mem(size => 8); }
+
+PMOVZXBW SSE4_1 00001111 00111000 00110000 !emit { data16(); modrm();
mem(size => 8); }
+PMOVZXBD SSE4_1 00001111 00111000 00110001 !emit { data16(); modrm();
mem(size => 4); }
+PMOVZXBQ SSE4_1 00001111 00111000 00110010 !emit { data16(); modrm();
mem(size => 2); }
+PMOVZXWD SSE4_1 00001111 00111000 00110011 !emit { data16(); modrm();
mem(size => 8); }
+PMOVZXWQ SSE4_1 00001111 00111000 00110100 !emit { data16(); modrm();
mem(size => 4); }
+PMOVZXDQ SSE4_1 00001111 00111000 00110101 !emit { data16(); modrm();
mem(size => 8); }
+
CVTPI2PS SSE 00001111 00101010 !emit { modrm(); mem(size => 8); }
CVTSI2SS SSE 00001111 00101010 !emit { rep(); modrm(); mem(size =>
4); }
CVTSI2SS_64 SSE 00001111 00101010 !emit { rep(); rex(w => 1); modrm();
mem(size => 8); }
@@ -383,6 +451,7 @@ MOVNTI SSE2 00001111 11000011 !emit { modrm(mod
=> ~MOD_DIRECT); mem
MOVNTI_64 SSE2 00001111 11000011 !emit { rex(w => 1); modrm(mod =>
~MOD_DIRECT); mem(size => 8); }
MOVNTQ SSE 00001111 11100111 !emit { modrm(mod => ~MOD_DIRECT);
mem(size => 8); }
MOVNTDQ SSE2 00001111 11100111 !emit { data16(); modrm(mod =>
~MOD_DIRECT); mem(size => 16, align => 16); }
+MOVNTDQA SSE4_1 00001111 00111000 00101010 !emit { data16(); modrm(mod
=> ~MOD_DIRECT); mem(size => 16, align => 16); }
PREFETCHT0 SSE 00001111 00011000 !emit { modrm(mod => ~MOD_DIRECT,
reg => 1); mem(size => 1); }
PREFETCHT1 SSE 00001111 00011000 !emit { modrm(mod => ~MOD_DIRECT,
reg => 2); mem(size => 1); }
--
2.20.1
- Re: [Qemu-devel] [RISU RFC PATCH v2 06/14] x86.risu: add MMX instructions, (continued)
[Qemu-devel] [RISU RFC PATCH v2 07/14] x86.risu: add SSE instructions, Jan Bobek, 2019/07/01
[Qemu-devel] [RISU RFC PATCH v2 09/14] x86.risu: add SSE3 instructions, Jan Bobek, 2019/07/01
[Qemu-devel] [RISU RFC PATCH v2 08/14] x86.risu: add SSE2 instructions, Jan Bobek, 2019/07/01
[Qemu-devel] [RISU RFC PATCH v2 10/14] x86.risu: add SSSE3 instructions, Jan Bobek, 2019/07/01
[Qemu-devel] [RISU RFC PATCH v2 11/14] x86.risu: add SSE4.1 and SSE4.2 instructions,
Jan Bobek <=
[Qemu-devel] [RISU RFC PATCH v2 13/14] x86.risu: add AVX instructions, Jan Bobek, 2019/07/01
[Qemu-devel] [RISU RFC PATCH v2 14/14] x86.risu: add AVX2 instructions, Jan Bobek, 2019/07/01