Re: [Qemu-devel] [PATCH for-4.1 v3 12/17] tcg/ppc: Initial backend support for Altivec

[Mark Cave-Ayland]

On 26/06/2019 19:36, BALATON Zoltan wrote:

> On Tue, 19 Mar 2019, Richard Henderson wrote:
>> diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
>> index ec8e336be8..70a64dd214 100644
>> --- a/tcg/ppc/tcg-target.inc.c
>> +++ b/tcg/ppc/tcg-target.inc.c
>> @@ -42,6 +42,9 @@
>> # define TCG_REG_TMP1   TCG_REG_R12
>> #endif
>>
>> +#define TCG_VEC_TMP1    TCG_REG_V0
>> +#define TCG_VEC_TMP2    TCG_REG_V1
>> +
>> #define TCG_REG_TB     TCG_REG_R31
>> #define USE_REG_TB     (TCG_TARGET_REG_BITS == 64)
>>
>> @@ -61,6 +64,7 @@
>>
>> static tcg_insn_unit *tb_ret_addr;
>>
>> +bool have_isa_altivec;
>> bool have_isa_2_06;
>> bool have_isa_3_00;
>>
>> @@ -72,39 +76,15 @@ bool have_isa_3_00;
>> #endif
>>
>> #ifdef CONFIG_DEBUG_TCG
>> -static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
>> -    "r0",
>> -    "r1",
>> -    "r2",
>> -    "r3",
>> -    "r4",
>> -    "r5",
>> -    "r6",
>> -    "r7",
>> -    "r8",
>> -    "r9",
>> -    "r10",
>> -    "r11",
>> -    "r12",
>> -    "r13",
>> -    "r14",
>> -    "r15",
>> -    "r16",
>> -    "r17",
>> -    "r18",
>> -    "r19",
>> -    "r20",
>> -    "r21",
>> -    "r22",
>> -    "r23",
>> -    "r24",
>> -    "r25",
>> -    "r26",
>> -    "r27",
>> -    "r28",
>> -    "r29",
>> -    "r30",
>> -    "r31"
>> +static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = {
>> +    "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
>> +    "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
>> +    "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
>> +    "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
>> +    "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
>> +    "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",
>> +    "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
>> +    "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
>> };
>> #endif
>>
>> @@ -139,6 +119,26 @@ static const int tcg_target_reg_alloc_order[] = {
>>     TCG_REG_R5,
>>     TCG_REG_R4,
>>     TCG_REG_R3,
> 
> Purely guessing without knowing anything about this but would removing 
> TCG_REG_R2
> from this tcg_target_reg_alloc_order[] list help? Question is why it was not a
> problem before?

Thanks for the suggestion, but I've just tried it and it doesn't seem to make 
any
difference :(


ATB,

Mark.