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[Qemu-devel] [PATCH v3 1/5] tricore: add FTOIZ instruction
From: |
David Brenken |
Subject: |
[Qemu-devel] [PATCH v3 1/5] tricore: add FTOIZ instruction |
Date: |
Mon, 24 Jun 2019 09:03:35 +0200 |
From: David Brenken <address@hidden>
Signed-off-by: Andreas Konopik <address@hidden>
Signed-off-by: David Brenken <address@hidden>
Signed-off-by: Georg Hofstetter <address@hidden>
Signed-off-by: Robert Rasche <address@hidden>
Signed-off-by: Lars Biermanski <address@hidden>
Reviewed-by: Bastian Koppelmann <address@hidden>
---
target/tricore/fpu_helper.c | 25 +++++++++++++++++++++++++
target/tricore/helper.h | 1 +
target/tricore/translate.c | 3 +++
3 files changed, 29 insertions(+)
diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index d8a6c0d25b..f079d9e939 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -303,6 +303,31 @@ uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg)
return (uint32_t)f_result;
}
+uint32_t helper_ftoiz(CPUTriCoreState *env, uint32_t arg)
+{
+ float32 f_arg = make_float32(arg);
+ uint32_t result;
+ int32_t flags;
+
+ result = float32_to_int32_round_to_zero(f_arg, &env->fp_status);
+
+ flags = f_get_excp_flags(env);
+ if (flags & float_flag_invalid) {
+ flags &= ~float_flag_inexact;
+ if (float32_is_any_nan(f_arg)) {
+ result = 0;
+ }
+ }
+
+ if (flags) {
+ f_update_psw_flags(env, flags);
+ } else {
+ env->FPU_FS = 0;
+ }
+
+ return result;
+}
+
uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg)
{
float32 f_arg = make_float32(arg);
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index f60e81096b..16b62edf7f 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -111,6 +111,7 @@ DEF_HELPER_4(fmsub, i32, env, i32, i32, i32)
DEF_HELPER_3(fcmp, i32, env, i32, i32)
DEF_HELPER_2(ftoi, i32, env, i32)
DEF_HELPER_2(itof, i32, env, i32)
+DEF_HELPER_2(ftoiz, i32, env, i32)
DEF_HELPER_2(ftouz, i32, env, i32)
DEF_HELPER_2(updfl, void, env, i32)
/* dvinit */
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 06c4485e55..5e1c4f54b9 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6747,6 +6747,9 @@ static void decode_rr_divide(CPUTriCoreState *env,
DisasContext *ctx)
case OPC2_32_RR_UPDFL:
gen_helper_updfl(cpu_env, cpu_gpr_d[r1]);
break;
+ case OPC2_32_RR_FTOIZ:
+ gen_helper_ftoiz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
--
2.22.0.windows.1
- [Qemu-devel] [PATCH v3 0/5] tricore: adding new instructions and fixing, David Brenken, 2019/06/24
- [Qemu-devel] [PATCH v3 2/5] tricore: add UTOF instruction, David Brenken, 2019/06/24
- [Qemu-devel] [PATCH v3 4/5] tricore: sync ctx.hflags with tb->flags, David Brenken, 2019/06/24
- [Qemu-devel] [PATCH v3 5/5] tricore: add QSEED instruction, David Brenken, 2019/06/24
- [Qemu-devel] [PATCH v3 1/5] tricore: add FTOIZ instruction,
David Brenken <=
- [Qemu-devel] [PATCH v3 3/5] tricore: fix RRPW_INSERT instruction, David Brenken, 2019/06/24
- Re: [Qemu-devel] [PATCH v3 0/5] tricore: adding new instructions and fixing, no-reply, 2019/06/24
- Re: [Qemu-devel] [PATCH v3 0/5] tricore: adding new instructions and fixing, no-reply, 2019/06/24
- Re: [Qemu-devel] [PATCH v3 0/5] tricore: adding new instructions and fixing, Bastian Koppelmann, 2019/06/25