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Re: [Qemu-devel] [PATCH v3 5/9] tests/x86-cpuid: Update testcases in tes
From: |
Eduardo Habkost |
Subject: |
Re: [Qemu-devel] [PATCH v3 5/9] tests/x86-cpuid: Update testcases in test_topo_bits() with multiple dies |
Date: |
Wed, 19 Jun 2019 16:10:23 -0300 |
On Wed, Jun 12, 2019 at 04:41:00PM +0800, Like Xu wrote:
> The corresponding topo_bits tests are updated to support die configurations.
>
> Signed-off-by: Like Xu <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
This probably should be squashed into patch 4/9 to keep
bisectability. I can do this while committing.
> ---
> tests/test-x86-cpuid.c | 84 ++++++++++++++++++++++--------------------
> 1 file changed, 45 insertions(+), 39 deletions(-)
>
> diff --git a/tests/test-x86-cpuid.c b/tests/test-x86-cpuid.c
> index ff225006e4..1942287f33 100644
> --- a/tests/test-x86-cpuid.c
> +++ b/tests/test-x86-cpuid.c
> @@ -28,74 +28,80 @@
>
> static void test_topo_bits(void)
> {
> - /* simple tests for 1 thread per core, 1 core per socket */
> - g_assert_cmpuint(apicid_smt_width(1, 1), ==, 0);
> - g_assert_cmpuint(apicid_core_width(1, 1), ==, 0);
> + /* simple tests for 1 thread per core, 1 core per die, 1 die per package
> */
> + g_assert_cmpuint(apicid_smt_width(1, 1, 1), ==, 0);
> + g_assert_cmpuint(apicid_core_width(1, 1, 1), ==, 0);
> + g_assert_cmpuint(apicid_die_width(1, 1, 1), ==, 0);
>
> - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 0), ==, 0);
> - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1), ==, 1);
> - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 2), ==, 2);
> - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 3), ==, 3);
> + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 0), ==, 0);
> + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 1), ==, 1);
> + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 2), ==, 2);
> + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 3), ==, 3);
>
>
> /* Test field width calculation for multiple values
> */
> - g_assert_cmpuint(apicid_smt_width(1, 2), ==, 1);
> - g_assert_cmpuint(apicid_smt_width(1, 3), ==, 2);
> - g_assert_cmpuint(apicid_smt_width(1, 4), ==, 2);
> + g_assert_cmpuint(apicid_smt_width(1, 1, 2), ==, 1);
> + g_assert_cmpuint(apicid_smt_width(1, 1, 3), ==, 2);
> + g_assert_cmpuint(apicid_smt_width(1, 1, 4), ==, 2);
>
> - g_assert_cmpuint(apicid_smt_width(1, 14), ==, 4);
> - g_assert_cmpuint(apicid_smt_width(1, 15), ==, 4);
> - g_assert_cmpuint(apicid_smt_width(1, 16), ==, 4);
> - g_assert_cmpuint(apicid_smt_width(1, 17), ==, 5);
> + g_assert_cmpuint(apicid_smt_width(1, 1, 14), ==, 4);
> + g_assert_cmpuint(apicid_smt_width(1, 1, 15), ==, 4);
> + g_assert_cmpuint(apicid_smt_width(1, 1, 16), ==, 4);
> + g_assert_cmpuint(apicid_smt_width(1, 1, 17), ==, 5);
>
>
> - g_assert_cmpuint(apicid_core_width(30, 2), ==, 5);
> - g_assert_cmpuint(apicid_core_width(31, 2), ==, 5);
> - g_assert_cmpuint(apicid_core_width(32, 2), ==, 5);
> - g_assert_cmpuint(apicid_core_width(33, 2), ==, 6);
> + g_assert_cmpuint(apicid_core_width(1, 30, 2), ==, 5);
> + g_assert_cmpuint(apicid_core_width(1, 31, 2), ==, 5);
> + g_assert_cmpuint(apicid_core_width(1, 32, 2), ==, 5);
> + g_assert_cmpuint(apicid_core_width(1, 33, 2), ==, 6);
>
> + g_assert_cmpuint(apicid_die_width(1, 30, 2), ==, 0);
> + g_assert_cmpuint(apicid_die_width(2, 30, 2), ==, 1);
> + g_assert_cmpuint(apicid_die_width(3, 30, 2), ==, 2);
> + g_assert_cmpuint(apicid_die_width(4, 30, 2), ==, 2);
>
> /* build a weird topology and see if IDs are calculated correctly
> */
>
> /* This will use 2 bits for thread ID and 3 bits for core ID
> */
> - g_assert_cmpuint(apicid_smt_width(6, 3), ==, 2);
> - g_assert_cmpuint(apicid_core_width(6, 3), ==, 3);
> - g_assert_cmpuint(apicid_pkg_offset(6, 3), ==, 5);
> + g_assert_cmpuint(apicid_smt_width(1, 6, 3), ==, 2);
> + g_assert_cmpuint(apicid_core_offset(1, 6, 3), ==, 2);
> + g_assert_cmpuint(apicid_die_offset(1, 6, 3), ==, 5);
> + g_assert_cmpuint(apicid_pkg_offset(1, 6, 3), ==, 5);
>
> - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 0), ==, 0);
> - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1), ==, 1);
> - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 2), ==, 2);
> + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 0), ==, 0);
> + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1), ==, 1);
> + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2), ==, 2);
>
> - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1 * 3 + 0), ==,
> + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 0), ==,
> (1 << 2) | 0);
> - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1 * 3 + 1), ==,
> + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 1), ==,
> (1 << 2) | 1);
> - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1 * 3 + 2), ==,
> + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 2), ==,
> (1 << 2) | 2);
>
> - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 2 * 3 + 0), ==,
> + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2 * 3 + 0), ==,
> (2 << 2) | 0);
> - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 2 * 3 + 1), ==,
> + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2 * 3 + 1), ==,
> (2 << 2) | 1);
> - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 2 * 3 + 2), ==,
> + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2 * 3 + 2), ==,
> (2 << 2) | 2);
>
> - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 5 * 3 + 0), ==,
> + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 5 * 3 + 0), ==,
> (5 << 2) | 0);
> - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 5 * 3 + 1), ==,
> + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 5 * 3 + 1), ==,
> (5 << 2) | 1);
> - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 5 * 3 + 2), ==,
> + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 5 * 3 + 2), ==,
> (5 << 2) | 2);
>
> - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1 * 6 * 3 + 0 * 3 + 0),
> ==,
> - (1 << 5));
> - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 1 * 6 * 3 + 1 * 3 + 1),
> ==,
> - (1 << 5) | (1 << 2) | 1);
> - g_assert_cmpuint(x86_apicid_from_cpu_idx(6, 3, 3 * 6 * 3 + 5 * 3 + 2),
> ==,
> - (3 << 5) | (5 << 2) | 2);
> + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3,
> + 1 * 6 * 3 + 0 * 3 + 0), ==, (1 << 5));
> + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3,
> + 1 * 6 * 3 + 1 * 3 + 1), ==, (1 << 5) | (1 << 2) | 1);
> + g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3,
> + 3 * 6 * 3 + 5 * 3 + 2), ==, (3 << 5) | (5 << 2) | 2);
> }
>
> int main(int argc, char **argv)
> --
> 2.21.0
>
--
Eduardo
- [Qemu-devel] [PATCH v3 0/9] Introduce cpu die topology and enable CPUID.1F for i386, Like Xu, 2019/06/12
- [Qemu-devel] [PATCH v3 7/9] target/i386: Support multi-dies when host doesn't support CPUID.1F, Like Xu, 2019/06/12
- [Qemu-devel] [PATCH v3 2/9] hw/i386: Adjust nr_dies with configured smp_dies for PCMachine, Like Xu, 2019/06/12
- [Qemu-devel] [PATCH v3 5/9] tests/x86-cpuid: Update testcases in test_topo_bits() with multiple dies, Like Xu, 2019/06/12
- Re: [Qemu-devel] [PATCH v3 5/9] tests/x86-cpuid: Update testcases in test_topo_bits() with multiple dies,
Eduardo Habkost <=
- [Qemu-devel] [PATCH v3 3/9] i386/cpu: Consolidate die-id validity in smp context, Like Xu, 2019/06/12
- [Qemu-devel] [PATCH v3 4/9] i386: Update new x86_apicid parsing rules with die_offset support, Like Xu, 2019/06/12
- [Qemu-devel] [PATCH v3 6/9] i386/cpu: Add CPUID.1F generation support for multi-dies PCMachine, Like Xu, 2019/06/12
- [Qemu-devel] [PATCH v3 8/9] machine: Refactor smp_parse() in vl.c as MachineClass::smp_parse(), Like Xu, 2019/06/12
- [Qemu-devel] [PATCH v3 9/9] vl.c: Add -smp, dies=* command line support and update doc, Like Xu, 2019/06/12