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[Qemu-devel] [PATCH v21 17/21] hw/rx: Restrict the RX62N microcontroller
From: |
Yoshinori Sato |
Subject: |
[Qemu-devel] [PATCH v21 17/21] hw/rx: Restrict the RX62N microcontroller to the RX62N CPU core |
Date: |
Tue, 18 Jun 2019 23:11:12 +0900 |
From: Philippe Mathieu-Daudé <address@hidden>
While the VIRT machine can use different microcontrollers,
the RX62N microcontroller is tied to the RX62N CPU core.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Yoshinori Sato <address@hidden>
---
hw/rx/rx-virt.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/hw/rx/rx-virt.c b/hw/rx/rx-virt.c
index 4cfe2e3123..9676a5e7bf 100644
--- a/hw/rx/rx-virt.c
+++ b/hw/rx/rx-virt.c
@@ -17,6 +17,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/error-report.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
@@ -56,6 +57,7 @@ static void rx_load_image(RXCPU *cpu, const char *filename,
static void rxvirt_init(MachineState *machine)
{
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
RX62NState *s = g_new(RX62NState, 1);
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *sdram = g_new(MemoryRegion, 1);
@@ -64,6 +66,12 @@ static void rxvirt_init(MachineState *machine)
void *dtb = NULL;
int dtb_size;
+ if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
+ error_report("This board can only be used with CPU %s",
+ mc->default_cpu_type);
+ exit(1);
+ }
+
/* Allocate memory space */
memory_region_init_ram(sdram, NULL, "sdram", 16 * MiB,
&error_fatal);
--
2.11.0
- [Qemu-devel] [PATCH v21 00/21] Add RX archtecture support, Yoshinori Sato, 2019/06/18
- [Qemu-devel] [PATCH v21 11/21] target/rx: Dump bytes for each insn during disassembly, Yoshinori Sato, 2019/06/18
- [Qemu-devel] [PATCH v21 08/21] target/rx: Disassemble rx_index_addr into a string, Yoshinori Sato, 2019/06/18
- [Qemu-devel] [PATCH v21 03/21] hw/registerfields.h: Add 8bit and 16bit register macros, Yoshinori Sato, 2019/06/18
- [Qemu-devel] [PATCH v21 02/21] qemu/bitops.h: Add extract8 and extract16, Yoshinori Sato, 2019/06/18
- [Qemu-devel] [PATCH v21 06/21] target/rx: CPU definition, Yoshinori Sato, 2019/06/18
- [Qemu-devel] [PATCH v21 05/21] target/rx: RX disassembler, Yoshinori Sato, 2019/06/18
- [Qemu-devel] [PATCH v21 09/21] target/rx: Emit all disassembly in one prt(), Yoshinori Sato, 2019/06/18
- [Qemu-devel] [PATCH v21 04/21] target/rx: CPU definition, Yoshinori Sato, 2019/06/18
- [Qemu-devel] [PATCH v21 15/21] hw/rx: RX Target hardware definition, Yoshinori Sato, 2019/06/18
- [Qemu-devel] [PATCH v21 17/21] hw/rx: Restrict the RX62N microcontroller to the RX62N CPU core,
Yoshinori Sato <=
- [Qemu-devel] [PATCH v21 09/21] target/rx: Replace operand with prt_ldmi in disassembler, Yoshinori Sato, 2019/06/18
- [Qemu-devel] [PATCH v21 10/21] target/rx: Use prt_ldmi for XCHG_mr disassembly, Yoshinori Sato, 2019/06/18
- [Qemu-devel] [PATCH v21 07/21] target/rx: Replace operand with prt_ldmi in disassembler, Yoshinori Sato, 2019/06/18
- [Qemu-devel] [PATCH v21 06/21] target/rx: Disassemble rx_index_addr into a string, Yoshinori Sato, 2019/06/18
- [Qemu-devel] [PATCH v21 01/21] MAINTAINERS: Add RX, Yoshinori Sato, 2019/06/18
- [Qemu-devel] [PATCH v21 11/21] target/rx: Emit all disassembly in one prt(), Yoshinori Sato, 2019/06/18
- [Qemu-devel] [PATCH v21 13/21] hw/timer: RX62N internal timer modules, Yoshinori Sato, 2019/06/18
- [Qemu-devel] [PATCH v21 12/21] target/rx: Collect all bytes during disassembly, Yoshinori Sato, 2019/06/18
- [Qemu-devel] [PATCH v21 14/21] hw/intc: RX62N interrupt controller (ICUa), Yoshinori Sato, 2019/06/18
- [Qemu-devel] [PATCH v21 15/21] hw/timer: RX62N internal timer modules, Yoshinori Sato, 2019/06/18