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[Qemu-devel] [PULL 04/24] hw/arm/boot: Honour image size field in AArch6
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 04/24] hw/arm/boot: Honour image size field in AArch64 Image format kernels |
Date: |
Mon, 17 Jun 2019 15:33:52 +0100 |
Since Linux v3.17, the kernel's Image header includes a field image_size,
which gives the total size of the kernel including unpopulated data
sections such as the BSS). If this is present, then return it from
load_aarch64_image() as the true size of the kernel rather than
just using the size of the Image file itself. This allows the code
which calculates where to put the initrd to avoid putting it in
the kernel's BSS area.
This means that we should be able to reliably load kernel images
which are larger than 128MB without accidentally putting the
initrd or dtb in locations that clash with the kernel itself.
Fixes: https://bugs.launchpad.net/qemu/+bug/1823998
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Mark Rutland <address@hidden>
Message-id: address@hidden
---
hw/arm/boot.c | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index a0e1110719e..b2f93f6beff 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -911,6 +911,7 @@ static uint64_t load_aarch64_image(const char *filename,
hwaddr mem_base,
hwaddr *entry, AddressSpace *as)
{
hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR;
+ uint64_t kernel_size = 0;
uint8_t *buffer;
int size;
@@ -938,7 +939,10 @@ static uint64_t load_aarch64_image(const char *filename,
hwaddr mem_base,
* is only valid if the image_size is non-zero.
*/
memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals));
- if (hdrvals[1] != 0) {
+
+ kernel_size = le64_to_cpu(hdrvals[1]);
+
+ if (kernel_size != 0) {
kernel_load_offset = le64_to_cpu(hdrvals[0]);
/*
@@ -956,12 +960,21 @@ static uint64_t load_aarch64_image(const char *filename,
hwaddr mem_base,
}
}
+ /*
+ * Kernels before v3.17 don't populate the image_size field, and
+ * raw images have no header. For those our best guess at the size
+ * is the size of the Image file itself.
+ */
+ if (kernel_size == 0) {
+ kernel_size = size;
+ }
+
*entry = mem_base + kernel_load_offset;
rom_add_blob_fixed_as(filename, buffer, size, *entry, as);
g_free(buffer);
- return size;
+ return kernel_size;
}
static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
--
2.20.1
- [Qemu-devel] [PULL 00/24] target-arm queue, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 01/24] hw/arm/boot: Don't assume RAM starts at address zero, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 03/24] hw/arm/boot: Avoid placing the initrd on top of the kernel, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 07/24] hw/arm/armv7m: Forward "vfp" and "dsp" properties to CPU, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 05/24] target/arm: Allow VFP and Neon to be disabled via a CPU property, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 02/24] hw/arm/boot: Diagnose layouts that put initrd or DTB off the end of RAM, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 06/24] target/arm: Allow M-profile CPUs to disable the DSP extension via CPU property, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 04/24] hw/arm/boot: Honour image size field in AArch64 Image format kernels,
Peter Maydell <=
- [Qemu-devel] [PULL 10/24] hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 09/24] hw/intc/arm_gicv3: Fix decoding of ID register range, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 08/24] hw/arm: Correctly disable FPU/DSP for some ARMSSE-based boards, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 11/24] target/arm: Move vfp_expand_imm() to translate.[ch], Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 15/24] target/arm: Stop using cpu_F0s for NEON_2RM_VRINT*, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 12/24] target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 13/24] target/arm: Stop using cpu_F0s for NEON_2RM_VABS_F, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 14/24] target/arm: Stop using cpu_F0s for NEON_2RM_VNEG_F, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 17/24] target/arm: Stop using cpu_F0s for NEON_2RM_VRECPE_F and NEON_2RM_VRSQRTE_F, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 16/24] target/arm: Stop using cpu_F0s for NEON_2RM_VCVT[ANPM][US], Peter Maydell, 2019/06/17