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Re: [Qemu-devel] [PATCH v21 4/7] target/avr: Add instruction translation
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v21 4/7] target/avr: Add instruction translation |
Date: |
Mon, 10 Jun 2019 08:09:48 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 |
On 6/6/19 12:30 PM, Michael Rolnik wrote:
> +void avr_cpu_tcg_init(void)
> +{
> + int i;
> +
> +#define AVR_REG_OFFS(x) offsetof(CPUAVRState, x)
> + cpu_pc = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(pc_w), "pc");
> + cpu_Cf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregC), "Cf");
> + cpu_Zf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregZ), "Zf");
> + cpu_Nf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregN), "Nf");
> + cpu_Vf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregV), "Vf");
> + cpu_Sf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregS), "Sf");
> + cpu_Hf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregH), "Hf");
> + cpu_Tf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregT), "Tf");
> + cpu_If = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregI), "If");
> + cpu_rampD = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampD),
> "rampD");
> + cpu_rampX = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampX),
> "rampX");
> + cpu_rampY = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampY),
> "rampY");
> + cpu_rampZ = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampZ),
> "rampZ");
> + cpu_eind = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(eind), "eind");
> + cpu_sp = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sp), "sp");
> + cpu_skip = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(skip), "skip");
> +
> + for (i = 0; i < 32; i++) {
> + char name[16];
> +
> + sprintf(name, "r[%d]", i);
> +
> + cpu_r[i] = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(r[i]), name);
> + }
> +}
These register names need to be permanently allocated.
I suggest
static const char reg_names[32][8] = {
"r[0]", "r[1]" ...
};
cpu_r[i] = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(r[i]),
reg_names[i]);
r~
[Qemu-devel] [PATCH v21 6/7] target/avr: Add example board configuration, Michael Rolnik, 2019/06/06
[Qemu-devel] [PATCH v21 5/7] target/avr: Add limited support for USART and 16 bit timer peripherals, Michael Rolnik, 2019/06/06