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[Qemu-devel] [PULL 39/39] tcg/arm: Remove mostly unreachable tlb special
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 39/39] tcg/arm: Remove mostly unreachable tlb special case |
Date: |
Sun, 9 Jun 2019 19:02:18 -0700 |
There was nothing armv7 specific about the bic+cmp sequence, however
looking at the set of guests more closely shows that the 8-bit immediate
operand for the bic can only be satisfied with one guest in tree:
baseline m-profile -- 10-bit pages with aligned 4-byte memory ops.
Therefore it does not seem useful to keep this path.
Acked-by: Alistair Francis <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/arm/tcg-target.inc.c | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index 276e843627..ece88dc2eb 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -1290,19 +1290,20 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg
addrlo, TCGReg addrhi,
tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1,
offsetof(CPUTLBEntry, addend));
- /* Check alignment, check comparators. */
- if (use_armv7_instructions) {
+ /*
+ * Check alignment, check comparators.
+ * Do this in no more than 3 insns. Use MOVW for v7, if possible,
+ * to reduce the number of sequential conditional instructions.
+ * Almost all guests have at least 4k pages, which means that we need
+ * to clear at least 9 bits even for an 8-byte memory, which means it
+ * isn't worth checking for an immediate operand for BIC.
+ */
+ if (use_armv7_instructions && TARGET_PAGE_BITS <= 16) {
tcg_target_ulong mask = ~(TARGET_PAGE_MASK | ((1 << a_bits) - 1));
- int rot = encode_imm(mask);
- if (rot >= 0) {
- tcg_out_dat_imm(s, COND_AL, ARITH_BIC, TCG_REG_TMP, addrlo,
- rotl(mask, rot) | (rot << 7));
- } else {
- tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask);
- tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP,
- addrlo, TCG_REG_TMP, 0);
- }
+ tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask);
+ tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP,
+ addrlo, TCG_REG_TMP, 0);
tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP, 0);
} else {
if (a_bits) {
--
2.17.1
- [Qemu-devel] [PULL 18/39] target/mips: Use env_cpu, env_archcpu, (continued)
- [Qemu-devel] [PULL 18/39] target/mips: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/09
- [Qemu-devel] [PULL 20/39] target/nios2: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/09
- [Qemu-devel] [PULL 23/39] target/riscv: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/09
- [Qemu-devel] [PULL 24/39] target/s390x: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/09
- [Qemu-devel] [PULL 26/39] target/sparc: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/09
- [Qemu-devel] [PULL 25/39] target/sh4: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/09
- [Qemu-devel] [PULL 22/39] target/ppc: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/09
- [Qemu-devel] [PULL 30/39] target/xtensa: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/09
- [Qemu-devel] [PULL 29/39] target/unicore32: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/09
- [Qemu-devel] [PULL 36/39] cpu: Remove CPU_COMMON, Richard Henderson, 2019/06/09
- [Qemu-devel] [PULL 39/39] tcg/arm: Remove mostly unreachable tlb special case,
Richard Henderson <=
- [Qemu-devel] [PULL 28/39] target/tricore: Use env_cpu, Richard Henderson, 2019/06/09
- [Qemu-devel] [PULL 33/39] cpu: Introduce CPUNegativeOffsetState, Richard Henderson, 2019/06/09
- [Qemu-devel] [PULL 34/39] cpu: Move icount_decr to CPUNegativeOffsetState, Richard Henderson, 2019/06/09
- [Qemu-devel] [PULL 27/39] target/tilegx: Use env_cpu, Richard Henderson, 2019/06/09
- [Qemu-devel] [PULL 32/39] cpu: Introduce cpu_set_cpustate_pointers, Richard Henderson, 2019/06/09
- [Qemu-devel] [PULL 31/39] cpu: Move ENV_OFFSET to exec/gen-icount.h, Richard Henderson, 2019/06/09
- [Qemu-devel] [PULL 35/39] cpu: Move the softmmu tlb to CPUNegativeOffsetState, Richard Henderson, 2019/06/09
- [Qemu-devel] [PULL 37/39] tcg/aarch64: Use LDP to load tlb mask+table, Richard Henderson, 2019/06/09
- [Qemu-devel] [PULL 38/39] tcg/arm: Use LDRD to load tlb mask+table, Richard Henderson, 2019/06/09
- Re: [Qemu-devel] [PULL 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState, no-reply, 2019/06/09