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[Qemu-devel] [PATCH v1 14/27] target/riscv: Generate illegal instruction
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From: |
Alistair Francis |
|
Subject: |
[Qemu-devel] [PATCH v1 14/27] target/riscv: Generate illegal instruction on WFI when V=1 |
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Date: |
Fri, 7 Jun 2019 14:56:04 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/op_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 644d0fb35f..e08bb8dd5a 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -130,9 +130,10 @@ void helper_wfi(CPURISCVState *env)
{
CPUState *cs = CPU(riscv_env_get_cpu(env));
- if (env->priv == PRV_S &&
+ if ((env->priv == PRV_S &&
env->priv_ver >= PRIV_VERSION_1_10_0 &&
- get_field(env->mstatus, MSTATUS_TW)) {
+ get_field(env->mstatus, MSTATUS_TW)) ||
+ riscv_cpu_virt_enabled(env)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
cs->halted = 1;
--
2.21.0
- [Qemu-devel] [PATCH v1 03/27] target/riscv: Add the virtulisation mode, (continued)
- [Qemu-devel] [PATCH v1 03/27] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/06/07
- [Qemu-devel] [PATCH v1 04/27] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/06/07
- [Qemu-devel] [PATCH v1 07/27] target/riscv: Remove strict perm checking for CSR R/W, Alistair Francis, 2019/06/07
- [Qemu-devel] [PATCH v1 05/27] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/06/07
- [Qemu-devel] [PATCH v1 06/27] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/06/07
- [Qemu-devel] [PATCH v1 08/27] target/riscv: Create function to test if FP is enabled, Alistair Francis, 2019/06/07
- [Qemu-devel] [PATCH v1 09/27] target/riscv: Add support for background interrupt setting, Alistair Francis, 2019/06/07
- [Qemu-devel] [PATCH v1 10/27] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/06/07
- [Qemu-devel] [PATCH v1 12/27] target/riscv: Add background register swapping function, Alistair Francis, 2019/06/07
- [Qemu-devel] [PATCH v1 13/27] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/06/07
- [Qemu-devel] [PATCH v1 14/27] target/riscv: Generate illegal instruction on WFI when V=1,
Alistair Francis <=
- [Qemu-devel] [PATCH v1 18/27] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/06/07
- [Qemu-devel] [PATCH v1 15/27] riscv: plic: Remove unused interrupt functions, Alistair Francis, 2019/06/07
- [Qemu-devel] [PATCH v1 17/27] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/06/07
- [Qemu-devel] [PATCH v1 11/27] target/riscv: Add background CSRs accesses, Alistair Francis, 2019/06/07
- [Qemu-devel] [PATCH v1 16/27] riscv: plic: Always set sip.SEIP bit for HS, Alistair Francis, 2019/06/07
- [Qemu-devel] [PATCH v1 19/27] target/riscv: Add hfence instructions, Alistair Francis, 2019/06/07
- [Qemu-devel] [PATCH v1 22/27] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2019/06/07
- [Qemu-devel] [PATCH v1 21/27] target/riscv: Mark both sstatus and bsstatus as dirty, Alistair Francis, 2019/06/07
- [Qemu-devel] [PATCH v1 25/27] target/riscv: Implement second stage MMU, Alistair Francis, 2019/06/07
- [Qemu-devel] [PATCH v1 24/27] target/riscv: Allow specifying number of MMU stages, Alistair Francis, 2019/06/07