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[Qemu-devel] [PULL v2 17/34] s390x/tcg: Implement VECTOR FP CONVERT FROM
From: |
Cornelia Huck |
Subject: |
[Qemu-devel] [PULL v2 17/34] s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BIT |
Date: |
Fri, 7 Jun 2019 16:17:10 +0200 |
From: David Hildenbrand <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
---
target/s390x/helper.h | 2 ++
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.inc.c | 3 +++
target/s390x/vec_fpu_helper.c | 23 +++++++++++++++++++++++
4 files changed, 30 insertions(+)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index a60f4c49fcf5..6fd996e924d0 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -268,6 +268,8 @@ DEF_HELPER_5(gvec_vfche64_cc, void, ptr, cptr, cptr, env,
i32)
DEF_HELPER_5(gvec_vfche64s_cc, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcdg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcdg64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vcdlg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vcdlg64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index d3386024c8f0..465b36dd70ba 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1220,6 +1220,8 @@
F(0xe7ea, VFCHE, VRR_c, V, 0, 0, 0, 0, vfc, 0, IF_VEC)
/* VECTOR FP CONVERT FROM FIXED 64-BIT */
F(0xe7c3, VCDG, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
+/* VECTOR FP CONVERT FROM LOGICAL 64-BIT */
+ F(0xe7c1, VCDLG, VRR_a, V, 0, 0, 0, 0, vcdg, 0, IF_VEC)
#ifndef CONFIG_USER_ONLY
/* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 6741b707ccc4..fa755cd1d648 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2657,6 +2657,9 @@ static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o)
case 0xc3:
fn = se ? gen_helper_gvec_vcdg64s : gen_helper_gvec_vcdg64;
break;
+ case 0xc1:
+ fn = se ? gen_helper_gvec_vcdlg64s : gen_helper_gvec_vcdlg64;
+ break;
default:
g_assert_not_reached();
}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index 53430c784375..181378e167d7 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -300,3 +300,26 @@ void HELPER(gvec_vcdg64s)(void *v1, const void *v2,
CPUS390XState *env,
vop64_2(v1, v2, env, true, XxC, erm, vcdg64, GETPC());
}
+
+static uint64_t vcdlg64(uint64_t a, float_status *s)
+{
+ return uint64_to_float64(a, s);
+}
+
+void HELPER(gvec_vcdlg64)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ const uint8_t erm = extract32(simd_data(desc), 4, 4);
+ const bool XxC = extract32(simd_data(desc), 2, 1);
+
+ vop64_2(v1, v2, env, false, XxC, erm, vcdlg64, GETPC());
+}
+
+void HELPER(gvec_vcdlg64s)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ const uint8_t erm = extract32(simd_data(desc), 4, 4);
+ const bool XxC = extract32(simd_data(desc), 2, 1);
+
+ vop64_2(v1, v2, env, true, XxC, erm, vcdlg64, GETPC());
+}
--
2.20.1
- [Qemu-devel] [PULL v2 07/34] s390x: Align vector registers to 16 bytes, (continued)
- [Qemu-devel] [PULL v2 07/34] s390x: Align vector registers to 16 bytes, Cornelia Huck, 2019/06/07
- [Qemu-devel] [PULL v2 08/34] s390x: Use uint64_t for vector registers, Cornelia Huck, 2019/06/07
- [Qemu-devel] [PULL v2 09/34] s390x/tcg: Fix max_byte detection for stfle, Cornelia Huck, 2019/06/07
- [Qemu-devel] [PULL v2 11/34] s390x/tcg: Introduce tcg_s390_vector_exception(), Cornelia Huck, 2019/06/07
- [Qemu-devel] [PULL v2 10/34] s390x/tcg: Store only the necessary amount of doublewords for STFLE, Cornelia Huck, 2019/06/07
- [Qemu-devel] [PULL v2 13/34] s390x/tcg: Implement VECTOR FP ADD, Cornelia Huck, 2019/06/07
- [Qemu-devel] [PULL v2 12/34] s390x/tcg: Export float_comp_to_cc() and float(32|64|128)_dcmask(), Cornelia Huck, 2019/06/07
- [Qemu-devel] [PULL v2 14/34] s390x/tcg: Implement VECTOR FP COMPARE (AND SIGNAL) SCALAR, Cornelia Huck, 2019/06/07
- [Qemu-devel] [PULL v2 15/34] s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL), Cornelia Huck, 2019/06/07
- [Qemu-devel] [PULL v2 16/34] s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BIT, Cornelia Huck, 2019/06/07
- [Qemu-devel] [PULL v2 17/34] s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BIT,
Cornelia Huck <=
- [Qemu-devel] [PULL v2 18/34] s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BIT, Cornelia Huck, 2019/06/07
- [Qemu-devel] [PULL v2 19/34] s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BIT, Cornelia Huck, 2019/06/07
- [Qemu-devel] [PULL v2 20/34] s390x/tcg: Implement VECTOR FP DIVIDE, Cornelia Huck, 2019/06/07
- [Qemu-devel] [PULL v2 22/34] s390x/tcg: Implement VECTOR LOAD LENGTHENED, Cornelia Huck, 2019/06/07
- [Qemu-devel] [PULL v2 21/34] s390x/tcg: Implement VECTOR LOAD FP INTEGER, Cornelia Huck, 2019/06/07
- [Qemu-devel] [PULL v2 23/34] s390x/tcg: Implement VECTOR LOAD ROUNDED, Cornelia Huck, 2019/06/07
- [Qemu-devel] [PULL v2 24/34] s390x/tcg: Implement VECTOR FP MULTIPLY, Cornelia Huck, 2019/06/07
- [Qemu-devel] [PULL v2 25/34] s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT), Cornelia Huck, 2019/06/07
- [Qemu-devel] [PULL v2 27/34] s390x/tcg: Implement VECTOR FP SQUARE ROOT, Cornelia Huck, 2019/06/07
- [Qemu-devel] [PULL v2 28/34] s390x/tcg: Implement VECTOR FP SUBTRACT, Cornelia Huck, 2019/06/07