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[Qemu-devel] [PATCH v4 17/39] target/microblaze: Use env_cpu, env_archcp
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v4 17/39] target/microblaze: Use env_cpu, env_archcpu |
Date: |
Tue, 4 Jun 2019 15:33:29 -0500 |
Cleanup in the boilerplate that each target must define.
Replace mb_env_get_cpu with env_archcpu. The combination
CPU(mb_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Move cpu_mmu_index below the include of "exec/cpu-all.h",
so that the definition of env_archcpu is available.
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/microblaze/cpu.h | 35 ++++++++++++++------------------
linux-user/microblaze/cpu_loop.c | 2 +-
target/microblaze/mmu.c | 5 ++---
target/microblaze/op_helper.c | 2 +-
target/microblaze/translate.c | 2 +-
5 files changed, 20 insertions(+), 26 deletions(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 6e68e00e1f..8402cc81f6 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -310,11 +310,6 @@ struct MicroBlazeCPU {
CPUMBState env;
};
-static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env)
-{
- return container_of(env, MicroBlazeCPU, env);
-}
-
#define ENV_OFFSET offsetof(MicroBlazeCPU, env)
void mb_cpu_do_interrupt(CPUState *cs);
@@ -344,21 +339,6 @@ int cpu_mb_signal_handler(int host_signum, void *pinfo,
#define MMU_USER_IDX 2
/* See NB_MMU_MODES further up the file. */
-static inline int cpu_mmu_index (CPUMBState *env, bool ifetch)
-{
- MicroBlazeCPU *cpu = mb_env_get_cpu(env);
-
- /* Are we in nommu mode?. */
- if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) {
- return MMU_NOMMU_IDX;
- }
-
- if (env->sregs[SR_MSR] & MSR_UM) {
- return MMU_USER_IDX;
- }
- return MMU_KERNEL_IDX;
-}
-
bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
@@ -384,4 +364,19 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr
physaddr, vaddr addr,
MemTxResult response, uintptr_t retaddr);
#endif
+static inline int cpu_mmu_index(CPUMBState *env, bool ifetch)
+{
+ MicroBlazeCPU *cpu = env_archcpu(env);
+
+ /* Are we in nommu mode?. */
+ if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) {
+ return MMU_NOMMU_IDX;
+ }
+
+ if (env->sregs[SR_MSR] & MSR_UM) {
+ return MMU_USER_IDX;
+ }
+ return MMU_KERNEL_IDX;
+}
+
#endif
diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c
index 076bdb9a61..a6ea71401d 100644
--- a/linux-user/microblaze/cpu_loop.c
+++ b/linux-user/microblaze/cpu_loop.c
@@ -23,7 +23,7 @@
void cpu_loop(CPUMBState *env)
{
- CPUState *cs = CPU(mb_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int trapnr, ret;
target_siginfo_t info;
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index fcf86b12d5..6763421ba2 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -34,7 +34,7 @@ static unsigned int tlb_decode_size(unsigned int f)
static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
{
- CPUState *cs = CPU(mb_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
struct microblaze_mmu *mmu = &env->mmu;
unsigned int tlb_size;
uint32_t tlb_tag, end, t;
@@ -228,7 +228,6 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn)
void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
{
- MicroBlazeCPU *cpu = mb_env_get_cpu(env);
uint64_t tmp64;
unsigned int i;
qemu_log_mask(CPU_LOG_MMU,
@@ -269,7 +268,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn,
uint32_t v)
/* Changes to the zone protection reg flush the QEMU TLB.
Fortunately, these are very uncommon. */
if (v != env->mmu.regs[rn]) {
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
env->mmu.regs[rn] = v;
break;
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
index b5dbb90d05..18677ddfca 100644
--- a/target/microblaze/op_helper.c
+++ b/target/microblaze/op_helper.c
@@ -65,7 +65,7 @@ uint32_t helper_get(uint32_t id, uint32_t ctrl)
void helper_raise_exception(CPUMBState *env, uint32_t index)
{
- CPUState *cs = CPU(mb_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = index;
cpu_loop_exit(cs);
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 885fc44b51..9ce65f3bcf 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1604,7 +1604,7 @@ static inline void decode(DisasContext *dc, uint32_t ir)
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
{
CPUMBState *env = cs->env_ptr;
- MicroBlazeCPU *cpu = mb_env_get_cpu(env);
+ MicroBlazeCPU *cpu = env_archcpu(env);
uint32_t pc_start;
struct DisasContext ctx;
struct DisasContext *dc = &ctx;
--
2.17.1
- [Qemu-devel] [PATCH v4 10/39] target/cris: Reindent mmu.c, (continued)
- [Qemu-devel] [PATCH v4 10/39] target/cris: Reindent mmu.c, Richard Henderson, 2019/06/04
- [Qemu-devel] [PATCH v4 09/39] target/arm: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/04
- [Qemu-devel] [PATCH v4 12/39] target/cris: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/04
- [Qemu-devel] [PATCH v4 11/39] target/cris: Reindent op_helper.c, Richard Henderson, 2019/06/04
- [Qemu-devel] [PATCH v4 13/39] target/hppa: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/04
- [Qemu-devel] [PATCH v4 06/39] cpu: Replace ENV_GET_CPU with env_cpu, Richard Henderson, 2019/06/04
- [Qemu-devel] [PATCH v4 15/39] target/lm32: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/04
- [Qemu-devel] [PATCH v4 14/39] target/i386: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/04
- [Qemu-devel] [PATCH v4 16/39] target/m68k: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/04
- [Qemu-devel] [PATCH v4 17/39] target/microblaze: Use env_cpu, env_archcpu,
Richard Henderson <=
- [Qemu-devel] [PATCH v4 19/39] target/moxie: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/04
- [Qemu-devel] [PATCH v4 18/39] target/mips: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/04
- [Qemu-devel] [PATCH v4 20/39] target/nios2: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/04
- [Qemu-devel] [PATCH v4 21/39] target/openrisc: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/04
- [Qemu-devel] [PATCH v4 23/39] target/riscv: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/04
- [Qemu-devel] [PATCH v4 25/39] target/sh4: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/04
- [Qemu-devel] [PATCH v4 22/39] target/ppc: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/04
- [Qemu-devel] [PATCH v4 24/39] target/s390x: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/04
- [Qemu-devel] [PATCH v4 26/39] target/sparc: Use env_cpu, env_archcpu, Richard Henderson, 2019/06/04
- [Qemu-devel] [PATCH v4 27/39] target/tilegx: Use env_cpu, Richard Henderson, 2019/06/04