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[Qemu-devel] [PULL 3/8] target/mips: Add emulation of MMI instruction PC
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 3/8] target/mips: Add emulation of MMI instruction PCPYUD |
Date: |
Sat, 1 Jun 2019 20:30:41 +0200 |
From: Mateja Marjanovic <address@hidden>
Add emulation of MMI instruction PCPYUD. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Reviewed-by: Aleksandar Rikalo <address@hidden>
Message-Id: <address@hidden>
---
target/mips/translate.c | 43 ++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b4fcbb1..e37722d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24458,6 +24458,45 @@ static void gen_mmi_pcpyld(DisasContext *ctx)
}
}
+/*
+ * PCPYUD rd, rs, rt
+ *
+ * Parallel Copy Upper Doubleword
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI | rs | rt | rd | PCPYUD | MMI3 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+static void gen_mmi_pcpyud(DisasContext *ctx)
+{
+ uint32_t rs, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ rs = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (rd == 0) {
+ /* nop */
+ } else {
+ if (rs == 0) {
+ tcg_gen_movi_i64(cpu_gpr[rd], 0);
+ } else {
+ tcg_gen_mov_i64(cpu_gpr[rd], cpu_mmr[rs]);
+ }
+ if (rt == 0) {
+ tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ } else {
+ if (rd != rt) {
+ tcg_gen_mov_i64(cpu_mmr[rd], cpu_mmr[rt]);
+ }
+ }
+ }
+}
+
#endif
@@ -27508,7 +27547,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext
*ctx)
case MMI_OPC_3_PINTEH: /* TODO: MMI_OPC_3_PINTEH */
case MMI_OPC_3_PMULTUW: /* TODO: MMI_OPC_3_PMULTUW */
case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */
- case MMI_OPC_3_PCPYUD: /* TODO: MMI_OPC_3_PCPYUD */
case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */
case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */
@@ -27518,6 +27556,9 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext
*ctx)
case MMI_OPC_3_PCPYH:
gen_mmi_pcpyh(ctx);
break;
+ case MMI_OPC_3_PCPYUD:
+ gen_mmi_pcpyud(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI3");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
- [Qemu-devel] [PULL 0/8] MIPS queue for June 1st, 2019, Aleksandar Markovic, 2019/06/01
- [Qemu-devel] [PULL 2/8] target/mips: Add emulation of MMI instruction PCPYLD, Aleksandar Markovic, 2019/06/01
- [Qemu-devel] [PULL 3/8] target/mips: Add emulation of MMI instruction PCPYUD,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 1/8] target/mips: Add emulation of MMI instruction PCPYH, Aleksandar Markovic, 2019/06/01
- [Qemu-devel] [PULL 7/8] target/mips: Clean up lmi_helper.c, Aleksandar Markovic, 2019/06/01
- [Qemu-devel] [PULL 8/8] target/mips: Improve performance of certain MSA instructions, Aleksandar Markovic, 2019/06/01
- [Qemu-devel] [PULL 6/8] target/mips: Clean up dsp_helper.c, Aleksandar Markovic, 2019/06/01
- [Qemu-devel] [PULL 5/8] tests/tcg: target/mips: Add tests for MSA bit set instructions, Aleksandar Markovic, 2019/06/01
- [Qemu-devel] [PULL 4/8] target/mips: Amend and cleanup MSA TCG tests, Aleksandar Markovic, 2019/06/01
- Re: [Qemu-devel] [PULL 0/8] MIPS queue for June 1st, 2019, Peter Maydell, 2019/06/03