Re: [Qemu-devel] [PATCH v15 00/12] Add RX archtecture support

[Yoshinori Sato]

On Wed, 22 May 2019 23:50:41 +0900,
Philippe Mathieu-Daudé wrote:
> 
> Hi Yoshinori,
> 
> On 5/22/19 4:29 PM, Yoshinori Sato wrote:
> > Hello.
> > This patch series is added Renesas RX target emulation.
> > 
> > Fix is bellow.
> > - Reorder patches.
> > - Rewrite renesas_cmt.
> >   Convert to RCMTChannelStatus
> > - Use CPUClass::tlb_fill
> > - Use tcg_gen_abs_i32
> > - Fix racw instructions.
> > - Cleanup for review comment.
> >   target/rx/helper.c - fix spelling.
> >   hw/intc/rx_icu.h - cleanup constant definition.
> >   hw/registerfields.h - fix macro definion order.
> 
> $ git backport-diff -u rx14 -r origin/master..rx15
> Key:
> [----] : patches are identical
> [####] : number of functional differences between upstream/downstream patch
> [down] : patch is downstream-only
> The flags [FC] indicate (F)unctional and (C)ontextual differences,
> respectively
> 
> 001/12:[----] [--] 'qemu/bitops.h: Add extract8 and extract16'
> 002/12:[0008] [FC] 'hw/registerfields.h: Add 8bit and 16bit register macros'
> 003/12:[0018] [FC] 'target/rx: TCG translation'
> 004/12:[0004] [FC] 'target/rx: TCG helper'
> 005/12:[0030] [FC] 'target/rx: CPU definition'
> 006/12:[----] [--] 'target/rx: RX disassembler'
> 007/12:[0003] [FC] 'hw/intc: RX62N interrupt controller (ICUa)'
> 008/12:[0178] [FC] 'hw/timer: RX62N internal timer modules'
> 009/12:[----] [--] 'hw/char: RX62N serial communication interface (SCI)'
> 010/12:[0004] [FC] 'hw/rx: RX Target hardware definition'
> 011/12:[----] [--] 'Add rx-softmmu'
> 012/12:[0004] [FC] 'MAINTAINERS: Add RX'
> 
> - you removed rx_abs(),
> - one change in trans_RACW()
> - fixed typos (Richard fixe them)
> - LOT of changes in the timer device, you added RCMTChannelState()
> 
> Hmm you did reset some of the R-b T-b tags.
> 
> 
> I guess Richard already prepared a pull request for your v14.
> 
> At this point I'd prefer the v14 get merged, and the v15 changes amended
> as new commits. This would ease review/testing.
> 
> Maybe Richard can still amend the 'trans_RACW' one-line fix on his pullreq.
> 
> Richard what's your take on this?
> 
> Regards,
> 
> Phil.

OK.
v15 fixes will be issued after merging.
Thanks.

> > My git repository is bellow.
> > git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git tags/rx-20190522
> > 
> > Testing binaries bellow.
> > u-boot
> > Download - https://osdn.net/users/ysato/pf/qemu/dl/u-boot.bin.gz
> > 
> > starting
> > $ gzip -d u-boot.bin.gz
> > $ qemu-system-rx -bios u-boot.bin
> > 
> > linux and pico-root (only sash)
> > Download - https://osdn.net/users/ysato/pf/qemu/dl/zImage (kernel)
> >            https://osdn.net/users/ysato/pf/qemu/dl/rx-qemu.dtb (DeviceTree)
> > 
> > starting
> > $ qemu-system-rx -kernel zImage -dtb rx-qemu.dtb -append "earlycon"
> > 
> > Yoshinori Sato (12):
> >   qemu/bitops.h: Add extract8 and extract16
> >   hw/registerfields.h: Add 8bit and 16bit register macros.
> >   target/rx: TCG translation
> >   target/rx: TCG helper
> >   target/rx: CPU definition
> >   target/rx: RX disassembler
> >   hw/intc: RX62N interrupt controller (ICUa)
> >   hw/timer: RX62N internal timer modules
> >   hw/char: RX62N serial communication interface (SCI)
> >   hw/rx: RX Target hardware definition
> >   Add rx-softmmu
> >   MAINTAINERS: Add RX
> 

-- 
Yosinori Sato