Re: [Qemu-devel] [RISU v2 05/11] risu_i386: implement missing CPU-specific functions

[Alex Bennée]

Jan Bobek <address@hidden> writes:

> risu_i386.c is expected to implement the following functions:
>
> - advance_pc
> - get_reginfo_paramreg, set_ucontext_paramreg
> - get_risuop
> - get_pc
>
> This patch adds the necessary code. We use EAX as the parameter
> register and opcode "UD1 %xxx,%eax" for triggering RISU actions.
>
> Suggested-by: Richard Henderson <address@hidden>
> Signed-off-by: Jan Bobek <address@hidden>

Reviewed-by: Alex Bennée <address@hidden>

> ---
>  risu_i386.c | 35 ++++++++++++++++++++++++++++++-----
>  1 file changed, 30 insertions(+), 5 deletions(-)
>
> diff --git a/risu_i386.c b/risu_i386.c
> index 2d2f325..06d95e5 100644
> --- a/risu_i386.c
> +++ b/risu_i386.c
> @@ -25,12 +25,37 @@ static int insn_is_ud2(uint32_t insn)
>
>  void advance_pc(void *vuc)
>  {
> -    /* We assume that this is either UD1 or UD2.
> -     * This would need tweaking if we want to test
> -     * expected undefs on x86.
> +    ucontext_t *uc = (ucontext_t *) vuc;
> +
> +    /*
> +     * We assume that this is UD1 as per get_risuop below.
> +     * This would need tweaking if we want to test expected undefs.
>       */
> -    ucontext_t *uc = vuc;
> -    uc->uc_mcontext.gregs[REG_EIP] += 2;
> +    uc->uc_mcontext.gregs[REG_E(IP)] += 3;
> +}
> +
> +void set_ucontext_paramreg(void *vuc, uint64_t value)
> +{
> +    ucontext_t *uc = (ucontext_t *) vuc;
> +    uc->uc_mcontext.gregs[REG_E(AX)] = value;
> +}
> +
> +uint64_t get_reginfo_paramreg(struct reginfo *ri)
> +{
> +    return ri->gregs[REG_E(AX)];
> +}
> +
> +int get_risuop(struct reginfo *ri)
> +{
> +    if ((ri->faulting_insn & 0xf8ffff) == 0xc0b90f) { /* UD1 %xxx,%eax */
> +        return (ri->faulting_insn >> 16) & 7;
> +    }
> +    return -1;
> +}
> +
> +uintptr_t get_pc(struct reginfo *ri)
> +{
> +    return ri->gregs[REG_E(IP)];
>  }
>
>  int send_register_info(int sock, void *uc)


--
Alex Bennée