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[Qemu-devel] [PATCH 05/16] tcg: Introduce do_op3_nofail for vector expan
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 05/16] tcg: Introduce do_op3_nofail for vector expansion |
Date: |
Sat, 18 May 2019 12:01:46 -0700 |
This makes do_op3 match do_op2 in allowing for failure,
and thus fall back expansions.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/tcg-op-vec.c | 45 +++++++++++++++++++++++++++------------------
1 file changed, 27 insertions(+), 18 deletions(-)
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index a888c02df8..004a34935b 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -562,7 +562,7 @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
}
}
-static void do_op3(unsigned vece, TCGv_vec r, TCGv_vec a,
+static bool do_op3(unsigned vece, TCGv_vec r, TCGv_vec a,
TCGv_vec b, TCGOpcode opc)
{
TCGTemp *rt = tcgv_vec_temp(r);
@@ -580,82 +580,91 @@ static void do_op3(unsigned vece, TCGv_vec r, TCGv_vec a,
can = tcg_can_emit_vec_op(opc, type, vece);
if (can > 0) {
vec_gen_3(opc, type, vece, ri, ai, bi);
- } else {
+ } else if (can < 0) {
const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
- tcg_debug_assert(can < 0);
tcg_expand_vec_op(opc, type, vece, ri, ai, bi);
tcg_swap_vecop_list(hold_list);
+ } else {
+ return false;
}
+ return true;
+}
+
+static void do_op3_nofail(unsigned vece, TCGv_vec r, TCGv_vec a,
+ TCGv_vec b, TCGOpcode opc)
+{
+ bool ok = do_op3(vece, r, a, b, opc);
+ tcg_debug_assert(ok);
}
void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
- do_op3(vece, r, a, b, INDEX_op_add_vec);
+ do_op3_nofail(vece, r, a, b, INDEX_op_add_vec);
}
void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
- do_op3(vece, r, a, b, INDEX_op_sub_vec);
+ do_op3_nofail(vece, r, a, b, INDEX_op_sub_vec);
}
void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
- do_op3(vece, r, a, b, INDEX_op_mul_vec);
+ do_op3_nofail(vece, r, a, b, INDEX_op_mul_vec);
}
void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
- do_op3(vece, r, a, b, INDEX_op_ssadd_vec);
+ do_op3_nofail(vece, r, a, b, INDEX_op_ssadd_vec);
}
void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
- do_op3(vece, r, a, b, INDEX_op_usadd_vec);
+ do_op3_nofail(vece, r, a, b, INDEX_op_usadd_vec);
}
void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
- do_op3(vece, r, a, b, INDEX_op_sssub_vec);
+ do_op3_nofail(vece, r, a, b, INDEX_op_sssub_vec);
}
void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
- do_op3(vece, r, a, b, INDEX_op_ussub_vec);
+ do_op3_nofail(vece, r, a, b, INDEX_op_ussub_vec);
}
void tcg_gen_smin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
- do_op3(vece, r, a, b, INDEX_op_smin_vec);
+ do_op3_nofail(vece, r, a, b, INDEX_op_smin_vec);
}
void tcg_gen_umin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
- do_op3(vece, r, a, b, INDEX_op_umin_vec);
+ do_op3_nofail(vece, r, a, b, INDEX_op_umin_vec);
}
void tcg_gen_smax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
- do_op3(vece, r, a, b, INDEX_op_smax_vec);
+ do_op3_nofail(vece, r, a, b, INDEX_op_smax_vec);
}
void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
- do_op3(vece, r, a, b, INDEX_op_umax_vec);
+ do_op3_nofail(vece, r, a, b, INDEX_op_umax_vec);
}
void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
- do_op3(vece, r, a, b, INDEX_op_shlv_vec);
+ do_op3_nofail(vece, r, a, b, INDEX_op_shlv_vec);
}
void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
- do_op3(vece, r, a, b, INDEX_op_shrv_vec);
+ do_op3_nofail(vece, r, a, b, INDEX_op_shrv_vec);
}
void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
- do_op3(vece, r, a, b, INDEX_op_sarv_vec);
+ do_op3_nofail(vece, r, a, b, INDEX_op_sarv_vec);
}
static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a,
@@ -691,7 +700,7 @@ static void do_shifts(unsigned vece, TCGv_vec r, TCGv_vec a,
} else {
tcg_gen_dup_i32_vec(vece, vec_s, s);
}
- do_op3(vece, r, a, vec_s, opc_v);
+ do_op3_nofail(vece, r, a, vec_s, opc_v);
tcg_temp_free_vec(vec_s);
}
tcg_swap_vecop_list(hold_list);
--
2.17.1
- [Qemu-devel] [PATCH 00/16] tcg: misc gvec improvments, Richard Henderson, 2019/05/18
- [Qemu-devel] [PATCH 11/16] tcg/aarch64: Support vector bitwise select value, Richard Henderson, 2019/05/18
- [Qemu-devel] [PATCH 07/16] tcg: Add TCG_OPF_NOT_PRESENT if TCG_TARGET_HAS_foo is negative, Richard Henderson, 2019/05/18
- [Qemu-devel] [PATCH 16/16] tcg/i386: Use MOVDQA for TCG_TYPE_V128 load/store, Richard Henderson, 2019/05/18
- [Qemu-devel] [PATCH 15/16] tcg/aarch64: Allow immediates for vector ORR and BIC, Richard Henderson, 2019/05/18
- [Qemu-devel] [PATCH 12/16] tcg/aarch64: Split up is_fimm, Richard Henderson, 2019/05/18
- [Qemu-devel] [PATCH 14/16] tcg/aarch64: Build vector immediates with two insns, Richard Henderson, 2019/05/18
- [Qemu-devel] [PATCH 10/16] tcg/i386: Use umin/umax in expanding unsigned compare, Richard Henderson, 2019/05/18
- [Qemu-devel] [PATCH 13/16] tcg/aarch64: Use MVNI in tcg_out_dupi_vec, Richard Henderson, 2019/05/18
- [Qemu-devel] [PATCH 09/16] tcg/i386: Remove expansion for missing minmax, Richard Henderson, 2019/05/18
- [Qemu-devel] [PATCH 05/16] tcg: Introduce do_op3_nofail for vector expansion,
Richard Henderson <=
- [Qemu-devel] [PATCH 08/16] tcg/i386: Support vector comparison select value, Richard Henderson, 2019/05/18
- [Qemu-devel] [PATCH 04/16] tcg: Add support for vector compare select, Richard Henderson, 2019/05/18
- [Qemu-devel] [PATCH 06/16] tcg: Expand vector minmax using cmp+cmpsel, Richard Henderson, 2019/05/18
- [Qemu-devel] [PATCH 01/16] tcg/i386: Fix dupi/dupm for avx1 and 32-bit hosts, Richard Henderson, 2019/05/18
- [Qemu-devel] [PATCH 03/16] tcg: Add support for vector bitwise select, Richard Henderson, 2019/05/18
- [Qemu-devel] [PATCH 02/16] tcg: Fix missing checks and clears in tcg_gen_gvec_dup_mem, Richard Henderson, 2019/05/18