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[Qemu-devel] [PULL 08/31] tcg: Support cross-class moves without instruc
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 08/31] tcg: Support cross-class moves without instruction support |
Date: |
Mon, 13 May 2019 17:05:17 -0700 |
PowerPC Altivec does not support direct moves between vector registers
and general registers. So when tcg_out_mov fails, we can use the
backing memory for the temporary to perform the move.
Acked-by: David Hildenbrand <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/tcg.c | 31 ++++++++++++++++++++++++++++---
1 file changed, 28 insertions(+), 3 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 8ed7cb8654..68d86361e2 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -3368,7 +3368,20 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp
*op)
ots->indirect_base);
}
if (!tcg_out_mov(s, otype, ots->reg, ts->reg)) {
- abort();
+ /*
+ * Cross register class move not supported.
+ * Store the source register into the destination slot
+ * and leave the destination temp as TEMP_VAL_MEM.
+ */
+ assert(!ots->fixed_reg);
+ if (!ts->mem_allocated) {
+ temp_allocate_frame(s, ots);
+ }
+ tcg_out_st(s, ts->type, ts->reg,
+ ots->mem_base->reg, ots->mem_offset);
+ ots->mem_coherent = 1;
+ temp_free_or_dead(s, ots, -1);
+ return;
}
}
ots->val_type = TEMP_VAL_REG;
@@ -3470,7 +3483,13 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp
*op)
reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs,
o_preferred_regs, ts->indirect_base);
if (!tcg_out_mov(s, ts->type, reg, ts->reg)) {
- abort();
+ /*
+ * Cross register class move not supported. Sync the
+ * temp back to its slot and load from there.
+ */
+ temp_sync(s, ts, i_allocated_regs, 0, 0);
+ tcg_out_ld(s, ts->type, reg,
+ ts->mem_base->reg, ts->mem_offset);
}
}
new_args[i] = reg;
@@ -3631,7 +3650,13 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
if (ts->reg != reg) {
tcg_reg_free(s, reg, allocated_regs);
if (!tcg_out_mov(s, ts->type, reg, ts->reg)) {
- abort();
+ /*
+ * Cross register class move not supported. Sync the
+ * temp back to its slot and load from there.
+ */
+ temp_sync(s, ts, allocated_regs, 0, 0);
+ tcg_out_ld(s, ts->type, reg,
+ ts->mem_base->reg, ts->mem_offset);
}
}
} else {
--
2.17.1
- [Qemu-devel] [PULL 28/31] target/s390x: Use tcg_gen_abs_i64, (continued)
- [Qemu-devel] [PULL 28/31] target/s390x: Use tcg_gen_abs_i64, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 30/31] target/xtensa: Use tcg_gen_abs_i32, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 23/31] tcg/aarch64: Support vector absolute value, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 11/31] tcg: Add tcg_out_dupm_vec to the backend interface, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 26/31] target/ppc: Use tcg_gen_abs_i32, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 18/31] tcg: Add gvec expanders for vector shift by scalar, Richard Henderson, 2019/05/14
- [Qemu-devel] [PULL 17/31] tcg/aarch64: Support vector variable shift opcodes, Richard Henderson, 2019/05/14
- [Qemu-devel] [PULL 20/31] tcg: Add support for integer absolute value, Richard Henderson, 2019/05/14
- [Qemu-devel] [PULL 06/31] tcg/arm: Use tcg_out_mov_reg in tcg_out_mov, Richard Henderson, 2019/05/14
- [Qemu-devel] [PULL 03/31] tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded, Richard Henderson, 2019/05/14
- [Qemu-devel] [PULL 08/31] tcg: Support cross-class moves without instruction support,
Richard Henderson <=
- [Qemu-devel] [PULL 16/31] tcg/i386: Support vector variable shift opcodes, Richard Henderson, 2019/05/14
- [Qemu-devel] [PULL 04/31] tcg: Specify optional vector requirements with a list, Richard Henderson, 2019/05/14
- Re: [Qemu-devel] [PULL 00/31] tcg: gvec improvments, Peter Maydell, 2019/05/14