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[Qemu-devel] [PULL 13/31] tcg/aarch64: Implement tcg_out_dupm_vec
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 13/31] tcg/aarch64: Implement tcg_out_dupm_vec |
Date: |
Mon, 13 May 2019 17:05:22 -0700 |
The LD1R instruction does all the work. Note that the only
useful addressing mode is a base register with no offset.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/aarch64/tcg-target.inc.c | 37 ++++++++++++++++++++++++++++++++++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 4a3cfa778a..b4585724d3 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -381,6 +381,9 @@ typedef enum {
I3207_BLR = 0xd63f0000,
I3207_RET = 0xd65f0000,
+ /* AdvSIMD load/store single structure. */
+ I3303_LD1R = 0x0d40c000,
+
/* Load literal for loading the address at pc-relative offset */
I3305_LDR = 0x58000000,
I3305_LDR_v64 = 0x5c000000,
@@ -566,7 +569,14 @@ static inline uint32_t tcg_in32(TCGContext *s)
#define tcg_out_insn(S, FMT, OP, ...) \
glue(tcg_out_insn_,FMT)(S, glue(glue(glue(I,FMT),_),OP), ## __VA_ARGS__)
-static void tcg_out_insn_3305(TCGContext *s, AArch64Insn insn, int imm19,
TCGReg rt)
+static void tcg_out_insn_3303(TCGContext *s, AArch64Insn insn, bool q,
+ TCGReg rt, TCGReg rn, unsigned size)
+{
+ tcg_out32(s, insn | (rt & 0x1f) | (rn << 5) | (size << 10) | (q << 30));
+}
+
+static void tcg_out_insn_3305(TCGContext *s, AArch64Insn insn,
+ int imm19, TCGReg rt)
{
tcg_out32(s, insn | (imm19 & 0x7ffff) << 5 | rt);
}
@@ -825,7 +835,30 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type,
unsigned vece,
static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
TCGReg r, TCGReg base, intptr_t offset)
{
- return false;
+ TCGReg temp = TCG_REG_TMP;
+
+ if (offset < -0xffffff || offset > 0xffffff) {
+ tcg_out_movi(s, TCG_TYPE_PTR, temp, offset);
+ tcg_out_insn(s, 3502, ADD, 1, temp, temp, base);
+ base = temp;
+ } else {
+ AArch64Insn add_insn = I3401_ADDI;
+
+ if (offset < 0) {
+ add_insn = I3401_SUBI;
+ offset = -offset;
+ }
+ if (offset & 0xfff000) {
+ tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff000);
+ base = temp;
+ }
+ if (offset & 0xfff) {
+ tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff);
+ base = temp;
+ }
+ }
+ tcg_out_insn(s, 3303, LD1R, type == TCG_TYPE_V128, r, base, vece);
+ return true;
}
static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
--
2.17.1
- [Qemu-devel] [PULL 00/31] tcg: gvec improvments, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 07/31] tcg: Return bool success from tcg_out_mov, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 13/31] tcg/aarch64: Implement tcg_out_dupm_vec,
Richard Henderson <=
- [Qemu-devel] [PULL 12/31] tcg/i386: Implement tcg_out_dupm_vec, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 19/31] tcg/i386: Support vector scalar shift opcodes, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 02/31] tcg: Do not recreate INDEX_op_neg_vec unless supported, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 10/31] tcg: Manually expand INDEX_op_dup_vec, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 29/31] target/tricore: Use tcg_gen_abs_tl, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 21/31] tcg: Add support for vector absolute value, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 09/31] tcg: Promote tcg_out_{dup, dupi}_vec to backend interface, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 22/31] tcg/i386: Support vector absolute value, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 31/31] tcg/aarch64: Do not advertise minmax for MO_64, Richard Henderson, 2019/05/13
- [Qemu-devel] [PULL 27/31] target/ppc: Use tcg_gen_abs_tl, Richard Henderson, 2019/05/13