[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 05/13] target/arm/kvm: Add kvm_arch_get/put_sve
From: |
Andrew Jones |
Subject: |
[Qemu-devel] [PATCH 05/13] target/arm/kvm: Add kvm_arch_get/put_sve |
Date: |
Sun, 12 May 2019 10:36:16 +0200 |
These are the SVE equivalents to kvm_arch_get/put_fpsimd.
Signed-off-by: Andrew Jones <address@hidden>
---
target/arm/kvm64.c | 127 +++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 123 insertions(+), 4 deletions(-)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 61947f3716e1..86362f4cd7d0 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -658,11 +658,12 @@ int kvm_arch_init_vcpu(CPUState *cs)
bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
{
/* Return true if the regidx is a register we should synchronize
- * via the cpreg_tuples array (ie is not a core reg we sync by
- * hand in kvm_arch_get/put_registers())
+ * via the cpreg_tuples array (ie is not a core or sve reg that
+ * we sync by hand in kvm_arch_get/put_registers())
*/
switch (regidx & KVM_REG_ARM_COPROC_MASK) {
case KVM_REG_ARM_CORE:
+ case KVM_REG_ARM64_SVE:
return false;
default:
return true;
@@ -748,6 +749,61 @@ static int kvm_arch_put_fpsimd(CPUState *cs)
return 0;
}
+static int kvm_arch_put_sve(CPUState *cs)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+ struct kvm_one_reg reg;
+ int n, ret;
+
+ for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; n++) {
+ uint64_t *q = aa64_vfp_qreg(env, n);
+#ifdef HOST_WORDS_BIGENDIAN
+ uint64_t d[ARM_MAX_VQ * 2];
+ int i;
+ for (i = 0; i < cpu->sve_max_vq * 2; i++) {
+ d[i] = q[cpu->sve_max_vq * 2 - 1 - i];
+ }
+ reg.addr = (uintptr_t)d;
+#else
+ reg.addr = (uintptr_t)q;
+#endif
+ reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
+ if (ret) {
+ return ret;
+ }
+ }
+
+ for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; n++) {
+ uint64_t *p = &env->vfp.pregs[n].p[0];
+#ifdef HOST_WORDS_BIGENDIAN
+ uint64_t d[ARM_MAX_VQ * 2];
+ int i;
+ for (i = 0; i < cpu->sve_max_vq * 2 / 8; i++) {
+ d[i] = p[cpu->sve_max_vq * 2 / 8 - 1 - i];
+ }
+ reg.addr = (uintptr_t)d;
+#else
+ reg.addr = (uintptr_t)p;
+#endif
+ reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
+ if (ret) {
+ return ret;
+ }
+ }
+
+ reg.addr = (uintptr_t)&env->vfp.pregs[FFR_PRED_NUM].p[0];
+ reg.id = KVM_REG_ARM64_SVE_FFR(0);
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
+ if (ret) {
+ return ret;
+ }
+
+ return 0;
+}
+
int kvm_arch_put_registers(CPUState *cs, int level)
{
struct kvm_one_reg reg;
@@ -842,7 +898,11 @@ int kvm_arch_put_registers(CPUState *cs, int level)
}
}
- ret = kvm_arch_put_fpsimd(cs);
+ if (!cpu_isar_feature(aa64_sve, cpu)) {
+ ret = kvm_arch_put_fpsimd(cs);
+ } else {
+ ret = kvm_arch_put_sve(cs);
+ }
if (ret) {
return ret;
}
@@ -905,6 +965,61 @@ static int kvm_arch_get_fpsimd(CPUState *cs)
return 0;
}
+static int kvm_arch_get_sve(CPUState *cs)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+ struct kvm_one_reg reg;
+ int n, ret;
+
+ for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; n++) {
+ uint64_t *q = aa64_vfp_qreg(env, n);
+ reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
+ reg.addr = (uintptr_t)q;
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
+ if (ret) {
+ return ret;
+ } else {
+#ifdef HOST_WORDS_BIGENDIAN
+ int i = 0, j = cpu->sve_max_vq * 2 - 1;
+ while (i < j) {
+ uint64_t t;
+ t = q[i], q[i] = q[j], q[j] = t;
+ ++i, --j;
+ }
+#endif
+ }
+ }
+
+ for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; n++) {
+ uint64_t *p = &env->vfp.pregs[n].p[0];
+ reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
+ reg.addr = (uintptr_t)p;
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
+ if (ret) {
+ return ret;
+ } else {
+#ifdef HOST_WORDS_BIGENDIAN
+ int i = 0, j = cpu->sve_max_vq * 2 / 8 - 1;
+ while (i < j) {
+ uint64_t t;
+ t = q[i], q[i] = q[j], q[j] = t;
+ ++i, --j;
+ }
+#endif
+ }
+ }
+
+ reg.addr = (uintptr_t)&env->vfp.pregs[FFR_PRED_NUM].p[0];
+ reg.id = KVM_REG_ARM64_SVE_FFR(0);
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
+ if (ret) {
+ return ret;
+ }
+
+ return 0;
+}
+
int kvm_arch_get_registers(CPUState *cs)
{
struct kvm_one_reg reg;
@@ -999,7 +1114,11 @@ int kvm_arch_get_registers(CPUState *cs)
env->spsr = env->banked_spsr[i];
}
- ret = kvm_arch_get_fpsimd(cs);
+ if (!cpu_isar_feature(aa64_sve, cpu)) {
+ ret = kvm_arch_get_fpsimd(cs);
+ } else {
+ ret = kvm_arch_get_sve(cs);
+ }
if (ret) {
return ret;
}
--
2.20.1
- Re: [Qemu-devel] [PATCH 07/13] target/arm/kvm: max cpu: Allow sve max vector length setting, (continued)
- [Qemu-devel] [PATCH 04/13] target/arm/kvm: Move the get/put of fpsimd registers out, Andrew Jones, 2019/05/12
- [Qemu-devel] [PATCH 06/13] target/arm/kvm: max cpu: Enable SVE when available, Andrew Jones, 2019/05/12
- [Qemu-devel] [PATCH 02/13] update-linux-headers: Add sve_context.h to asm-arm64, Andrew Jones, 2019/05/12
- [Qemu-devel] [PATCH 09/13] target/arm/kvm: Export kvm_arm_get_sve_vls, Andrew Jones, 2019/05/12
- [Qemu-devel] [PATCH 08/13] target/arm/monitor: Add query-sve-vector-lengths, Andrew Jones, 2019/05/12
- [Qemu-devel] [PATCH 05/13] target/arm/kvm: Add kvm_arch_get/put_sve,
Andrew Jones <=
- Re: [Qemu-devel] [PATCH 05/13] target/arm/kvm: Add kvm_arch_get/put_sve, Richard Henderson, 2019/05/13
- Re: [Qemu-devel] [PATCH 05/13] target/arm/kvm: Add kvm_arch_get/put_sve, Andrew Jones, 2019/05/13
- Re: [Qemu-devel] [PATCH 05/13] target/arm/kvm: Add kvm_arch_get/put_sve, Richard Henderson, 2019/05/13
Re: [Qemu-devel] [PATCH 05/13] target/arm/kvm: Add kvm_arch_get/put_sve, Dave Martin, 2019/05/13